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mb/starlabs/starbook/tgl: Alphabetize and group FSP UPDs

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Change-Id: I6bab0a316ea7d0f7dfbf599e5c08517cee559635
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2024-09-09 12:43:02 +01:00
commit 55e265ea39
1 changed files with 5 additions and 9 deletions
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14
src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
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@ -1,7 +1,10 @@
chip soc/intel/tigerlake
# CPU
# Enable Enhanced Intel SpeedStep
# FSP UPDs
register "eist_enable" = "true"
register "enable_c6dram" = "1"
register "CnviBtCore" = "true"
register "CnviBtAudioOffload" = "1"
register "SaGv" = "SaGv_Enabled"
# Graphics
# Not used but timings left for reference
@ -14,13 +17,6 @@ chip soc/intel/tigerlake
# .backlight_pwm_hz = 200, // PWM
# }"
# FSP Memory
register "CnviBtCore" = "true"
register "CnviBtAudioOffload" = "1"
register "enable_c6dram" = "1"
register "SaGv" = "SaGv_Enabled"
# FSP Silicon
# Serial I/O
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,