soc/amd/glinda/include/smu.h: Update mailbox register addresses
Signed-off-by: Avinash Munduru <AvinashMunduru@amd.com> Change-Id: I427186aa9f0fb0650b2ab8d6171a51a33edf2778 Tested-by: Avinash Munduru <Avinash.Munduru@amd.com> Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84384 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -6,8 +6,8 @@
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#define AMD_GLINDA_SMU_H
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/* SMU mailbox register offsets in SMN */
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#define SMN_SMU_MESG_ID 0x3b10528
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#define SMN_SMU_MESG_RESP 0x3b10578
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#define SMN_SMU_MESG_ID 0x3b10928
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#define SMN_SMU_MESG_RESP 0x3b10978
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#define SMN_SMU_MESG_ARGS_BASE 0x3b10998
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#define SMU_NUM_ARGS 6
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