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soc/intel/alderlake: Hook up PCIe Power Management to option API

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Hook up PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUBSTATE to the
option API.

This provides users an easy way to disable power saving options
that can limit performance.

Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81906
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2024-04-15 10:20:41 +01:00 • committed by Martin L Roth
commit 7d904cb7c6
1 changed files with 14 additions and 8 deletions
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22
src/soc/intel/alderlake/fsp_params.c
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@ -529,9 +529,12 @@ static void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg,
const struct pcie_rp_config *rp_cfg,
unsigned int index)
{
s_cfg->PcieRpEnableCpm[index] = CONFIG(PCIEXP_CLK_PM);
s_cfg->PcieRpAspm[index] = adl_aspm_control_to_upd(rp_cfg->pcie_rp_aspm);
s_cfg->PcieRpL1Substates[index] = adl_l1ss_control_to_upd(rp_cfg->PcieRpL1Substates);
s_cfg->PcieRpEnableCpm[index] =
get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM));
s_cfg->PcieRpAspm[index] =
adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm));
s_cfg->PcieRpL1Substates[index] =
adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates));
}
/*
@ -551,11 +554,14 @@ static void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg,
const struct pcie_rp_config *rp_cfg,
unsigned int index)
{
s_cfg->CpuPcieRpEnableCpm[index] = CONFIG(PCIEXP_CLK_PM);
s_cfg->CpuPcieClockGating[index] = CONFIG(PCIEXP_CLK_PM);
s_cfg->CpuPciePowerGating[index] = CONFIG(PCIEXP_CLK_PM);
s_cfg->CpuPcieRpAspm[index] = adl_aspm_control_to_upd(rp_cfg->pcie_rp_aspm);
s_cfg->CpuPcieRpL1Substates[index] = adl_l1ss_control_to_upd(rp_cfg->PcieRpL1Substates);
bool pciexp_clk_pm = get_uint_option("pciexp_clk_pm", CONFIG(PCIEXP_CLK_PM));
s_cfg->CpuPcieRpEnableCpm[index] = pciexp_clk_pm;
s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm;
s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm;
s_cfg->CpuPcieRpAspm[index] =
adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm));
s_cfg->CpuPcieRpL1Substates[index] =
adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates));
}
/* This function returns the VccIn Aux Imon IccMax values for ADL and RPL