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soc/intel/cannonlake,skylake: Fix locking SMRAM

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Intel TXT SINIT required the D_LCK bit set. Although coreboot
tries to set it, the bit ws still clear. The D_LCK bit has to be
set using I/O CF8/CFC cycle.

TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled

Change-Id: I03aff482b53ab7b0bcaccf18e47ad4c22b53583c
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
This commit is contained in:
Michał Żygowski 2024-08-01 11:37:24 +02:00 • committed by Felix Held
commit eee5c10c94
2 changed files with 6 additions and 6 deletions
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6
src/soc/intel/cannonlake/cpu.c
View file

@ -162,14 +162,14 @@ static void per_cpu_smm_trigger(void)
void smm_lock(void)
{
struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
/*
* LOCK the SMM memory window and enable normal SMM.
* After running this function, only a full reset can
* make the SMM registers writable again.
* make the SMM registers writable again. D_LCK bit
* requires the PCI 0xcf8/0xcfc I/O access.
*/
printk(BIOS_DEBUG, "Locking SMM.\n");
pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
pci_io_write_config8(SA_DEVFN_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
}
static void post_mp_init(void)

6
src/soc/intel/skylake/cpu.c
View file

@ -164,14 +164,14 @@ static void per_cpu_smm_trigger(void)
void smm_lock(void)
{
struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
/*
* LOCK the SMM memory window and enable normal SMM.
* After running this function, only a full reset can
* make the SMM registers writable again.
* make the SMM registers writable again. D_LCK bit
* requires the PCI 0xcf8/0xcfc I/O access.
*/
printk(BIOS_DEBUG, "Locking SMM.\n");
pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
pci_io_write_config8(SA_DEVFN_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
}
static void vmx_configure(void *unused)