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mb/starlabs/starbook/cml: Alphabetize and group FSP UPDs

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Change-Id: I063062d875be61875da136228db06a39bc434833
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Sean Rhodes 2024-09-09 12:36:58 +01:00 • committed by Felix Held
commit 4493f66904
1 changed files with 3 additions and 7 deletions
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10
src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
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@ -1,7 +1,8 @@
chip soc/intel/cannonlake
# CPU
# Enable Enhanced Intel SpeedStep
# FSP UPDs
register "eist_enable" = "true"
register "enable_c6dram" = "1"
register "SaGv" = "SaGv_Enabled"
# Graphics
# IGD Displays
@ -14,11 +15,6 @@ chip soc/intel/cannonlake
.backlight_pwm_hz = 200, // PWM
}"
# FSP Memory
register "enable_c6dram" = "1"
register "SaGv" = "SaGv_Enabled"
# FSP Silicon
# Serial I/O
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,