Introduce a new CBMEM ID, CBMEM_ID_BOOT_MODE (0x444D5442, "BTMD"),
to provide a dedicated storage location for the system's detected
boot mode (e.g., normal boot, low-battery, off-mode boot etc).
Storing the boot mode in CBMEM ensures that the initial detection
performed early in the boot process (e.g., in romstage by reading
PMIC logs) is securely passed to subsequent stages like ramstage,
where different boot modes require distinct logic paths.
Key changes:
- Define CBMEM_ID_BOOT_MODE in cbmem_id.h.
- Add "BOOT MODE" entry to the CBMEM_ID_TO_NAME_TABLE.
BUG=b:439819922
TEST=Verify boot mode stored in CBMEM.
Change-Id: I7ebf29385a99ac1be491bfefe1c74c8c9e58b55d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90175
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor the is_off_mode() detection API on the Bluey mainboard
to call the newly introduced SOC-specific PMIC function,
is_pon_on_ac().
This change delegates the complex Power-On (PON) log parsing and
PMIC register checking to the SOC layer, simplifying the mainboard
code base. The board layer now contains only the high-level policy
wrapper for detecting cable-power-on events.
This improves modularity and ensures the board code relies on the
correct hardware abstraction.
Key changes:
- Implement is_off_mode() as a simple wrapper around is_pon_on_ac()
(from the SOC PMIC library).
- Include soc/pmic.h to access the SOC's PMIC APIs.
- Expose is_off_mode() in board.h.
BUG=b:439819922
TEST=Verify boot mode on Google/Quenbi.
Change-Id: Ibc13c3ad96846cf5b3fb9bcf461e3f338ac9b8bd
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add the Power-On (PON) history log parsing and status API to the
SOC layer (soc/qualcomm/x1p42100/pmic.c).
This code is specific to the Qualcomm PMIC architecture (reading
registers for PON events and reasons), making it an SOC-specific
utility rather than a board-level policy. Moving it here improves
modularization and allows other X1p42100-based boards to reuse this
critical power management logic.
Key APIs introduced:
- pm_pon_read_pon_hist(): Reads the raw circular PON event log
from the PMIC, reverses the buffer to put the latest entry first.
- is_pon_on_ac(): Interprets the log to detect if the power-on
reason was due to AC/Cable Power (PON_CBLPWR_RSN).
Key changes:
- Create src/soc/qualcomm/x1p42100/include/soc/pmic.h with PON
definitions and API prototypes.
- Create src/soc/qualcomm/x1p42100/pmic.c containing the PON
log reading and parsing logic.
- Add pmic.c to the SOC's romstage build via Makefile.mk.
BUG=b:439819922
TEST=Verify off-mode charging behavior on Google/Quenbi.
Change-Id: I8cd1478b9f8d53519f603e8f5168d0a51fa54971
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90192
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new API, spmi_read_bytes(), to allow reading a
sequence of registers from a Qualcomm PMIC using the SPMI bus.
While the existing spmi_read8() is suitable for single-byte
access, reading large log areas (like the PON history log)
requires iterating over a contiguous block of addresses. This
new function encapsulates the required loop, calling spmi_read8()
sequentially for each address in the range.
This abstraction improves code cleanliness and makes high-level PMIC
log parsing much simpler.
Key changes:
- Define spmi_read_bytes() prototype in qcom_spmi.h.
- Implement spmi_read_bytes() in spmi.c to perform sequential
reads using spmi_read8().
BUG=b:439819922
TEST=Verify off-mode charging behavior on Google/Quenbi.
Change-Id: I6017336a882a8fa8d771b0127e78dd4f0fdbdd0e
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update the SPMI_ADDR macro to wrap both the slave and reg
arguments in parentheses.
The previous definition, ((slave << 16) | reg), led to incorrect
address calculation when the slave argument was an arithmetic or
logical expression (e.g., (a | b)), as the bit-shift operator (<<)
has higher precedence than the logical OR (|).
The revised macro guarantees that the full slave expression is
evaluated before the bit shift, ensuring correct SPMI register
address construction.
Key changes:
- Wrap slave and reg arguments in parentheses within
SPMI_ADDR definition.
BUG=b:439819922
TEST=Verify that the SPMI_ADDR output is correct.
e.g. SPMI_ADDR(0x02 | 0x01, 0x200)
Output before this change:
```
((0x02 | 0x01 << 16) | 0x200)
(0x02 | 0x010000 | 0x200)
(0x010202)
```
Output after this change:
```
(((0x02 | 0x01) << 16) | 0x200)
(((0x03) << 16) | 0x200)
((0x030000) | 0x200)
(0x030200)
```
Change-Id: I58b36b62f0b5a59c03a1c1d08640fe9086d81d7a
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90198
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the GT domain Thermal Design Current (TDC) value for the
PTL_TDC_1 SKU from 15A to 23A to align with the latest hardware
specifications. The previous value was inconsistent with the intended
power map, which could lead to incorrect power delivery settings and
potential system instability. This change ensures compliance with
Document #813289, revision 2.1.
Change-Id: Ib6b4ddc422de62585658b5e8464d598762b947ee
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Align the IA domain Thermal Design Current (TDC) value for PTL_TDC_2
with Document #813289 power map revision 2.1. The previous value 23A did
not match the updated specification, which now requires 28A. This change
ensures that the firmware correctly reflects the hardware power limits
for this SKU, preventing potential power delivery issues and improving
system stability.
Change-Id: I16bb510b8ec2ad1ffdeba20bfe26d0cbad209088
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89935
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SKU_7 ICC Max and TDC were not accurate. This commit aligns SKU_7
settings with document #813278 - Panther Lake H Platform Power Map
2.1.1.
Change-Id: Ia66ca5c0d2dc1ba0f0cf3b21476e83923e49969e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit refactors the Panther Lake SoC power mapping and
configuration to support distinct Thermal Design Current (TDC) settings
for each TDP variant and SKU. Previously, TDC values were mapped
directly to SKUs, which limited flexibility and could lead to incorrect
current settings for CPUs with the same SKU but different TDP
requirements.
TEST=On a Fatcat device with a 25W TDP, the FSP logs show that the
appropriate TDC settings were applied.
Change-Id: Ie645110e9ff200ecb601faf427958ded731fb22b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89932
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Because the proto and evt build use the same panel but different
controllers, so add proto touch panel address to fit two controllers.
BUG=b:452216678
TEST=Build FW and boot to OS, check touch function works.
Change-Id: Ia9a3764ffe85aa69ba1c4c3f4ae8fd2717e1e570
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Its useful if you have some binaries downstream which are not published
yet.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I00f67e6eb93af095e3ae1f4851d13cd7666a9851
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90180
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the option to enable M.2 SDD slot to Kconfig file instead of using
a macro. Its already used like a Kconfig option later on, so the if
condition actually works now.
Change-Id: I104eae5501da6ed1fe43039f88d6722c1e54e82d
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove the gpio function calls from ec code and mode to early gpio file.
Change-Id: I941828808bdcdac00ab59d48907da1f70024d6e0
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87442
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove duplicate code and make it into a single function to
read the board revision from ec.
Change-Id: If7f3e7eda2c43417639494880a080fa472474cab
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87441
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If XGBE is used on the platform, it can be configured to match different
use cases.
Change-Id: Ia6f7c2b836050e52bfb1d9ff64745d83715c874b
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90104
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add FSP folder for Renoir and include it in the build from soc/cezanne
path. Cezanne and Renoir are very similar but there are still enough
changes to justify a separate vendorcode directory.
Change-Id: Id7f51a70c02ea632d87a635e92a6c422ac369bef
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Commit 04778ddd38 ("drivers/option/cfr: Remove old sm_object from
constructor") updated the function signature for CFR callbacks, but the
commits adding the fan and backlight controls were merged afterwards
without being adjusted accordingly. Do so here.
TEST=build/boot google/link with these CFR options enabled.
Change-Id: I9ea5224a820b014c4c8edb93e8a6b336ea6f58d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
This commit adds wake functionality to the CNVi Bluetooth device by
registering to "GPE0_PME_B0" using the common CNVi block.
BUG=454341255
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: I4bcbb34e1d53b3438f9e9f2b39f09d91e8dc7110
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89982
Reviewed-by: P, Usha <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure and enable the PCIe root ports and associated clocks for the
mc_ehl6 mainboard. This is necessary because the PCIe configuration
differs from the mc_ehl2 baseboard.
TEST=Boot into the OS and verify that all expected PCIe devices are
correctly detected.
Change-Id: Ie5ac3d437088d1db08f869317ef3e5712c3baa3e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This new mainboard variant for the Siemens mc_ehl6 is initially based on
a direct copy of the mc_ehl2 configuration. This commit contains the
basic board setup with only minimal changes to enable the new variant.
Further specific adaptations for the mc_ehl6 hardware will be handled
in subsequent commits.
Change-Id: Ifcc730da492edb084e67762ce643f27b1a2576b0
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Now that we use the WATCHDOG_TOMBSTONE section to store the watchdog
event magic, there is no need to ask EC for the last reset reason. In
fact, with MEDIATEK_WDT_RESET_BY_SW enabled, EC doesn't even record the
watchdog reset reason.
Enable CHROMEOS_USE_EC_WATCHDOG_FLAG only if MEDIATEK_WDT_RESET_BY_SW is
disabled.
BUG=b:433636690
TEST=emerge-skywalker coreboot
TEST="elogtool list" contained "Hardware watchdog reset"
BRANCH=skywalker
Change-Id: Iac6ec72d5c148244ccbd7d1b02af78c359897d7d
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90174
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the watchdog timeout triggers a reset, the CPU will return to the
default frequency. If there is a mismatch between voltage and frequency,
the device will fail to reboot. Therefore, the kernel configuration
"mediatek,disable-extrst" is removed for MT8189, meaning the watchdog
timeout will trigger external reset, by notifying PMIC and EC via
AP_PMIC_WDTRST_L.
As we want to keep the watchdog status registers until coreboot runs,
the MT8189's EC simply ignores the external reset signal
AP_PMIC_WDTRST_L. Because EC ignores it, coreboot has to trigger the
secondary reset by another method other than watchdog hardware.
Therefore, introduce a Kconfig option MEDIATEK_WDT_RESET_BY_SW to
trigger the secondary reset by board_reset(), which is often implemented
by asserting a GPIO (for example GPIO_AP_EC_WARM_RST_REQ for MT8189).
BUG=b:433636690
TEST=emerge-skywalker coreboot
BRANCH=skywalker
Change-Id: Ib4c698bfd1b85705be05f40f385f4e252975c319
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90172
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
The purpose of the WATCHDOG_TOMBSTONE section is to temporarily record
the watchdog timeout event, before triggering the reboot. Then, in the
next boot, if WATCHDOG_TOMBSTONE contains the watchdog event magic, then
a watchdog event will be added to the event log.
The flow relies on the fact that the WATCHDOG_TOMBSTONE section can be
preserved across AP resets. However, for MT8189, the whole SRAM region
will be powered down during AP reset via GPIO AP_SYSRST_ODL (SYSRSTB).
Fortunately, the Kconfig option CHROMEOS_USE_EC_WATCHDOG_FLAG is also
enabled. Therefore, even if WATCHDOG_TOMBSTONE data is cleared, the
elog_handle_watchdog_tombstone() function can still obtain the correct
watchdog reset reason from EC.
On MT8189, L3C (used as SRAM_L2C) is powered on by default. Also, per
MT8189 PMIC configuration, a SYSRSTB reset will retain the L3C power.
Therefore, region data in SRAM_L2C can be preserved across AP resets.
Fix the WATCHDOG_TOMBSTONE preservation by moving it to SRAM_L2C.
Reduce PRERAM_CBMEM_CONSOLE by 1K for WATCHDOG_TOMBSTONE.
BUG=b:433636690, b:456672760
TEST=emerge-skywalker coreboot
TEST=watchdog event added to eventlog on WDT timeout
TEST=cbmem logs preserved on WDT timeout
BRANCH=skywalker
Change-Id: Id1cfc2700301ebb0b6399356b884b2473c883445
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Update EN_SPK_PA pin configuration based on the schematic to enable speaker function.
schematics: RUBY_EVT_0902_2112.pdf
BUG=b:452216678
TEST=Build FW and boot to OS, verify that the speaker is functioning
by playing a YouTube video.
Change-Id: Iabb3e9d214841aaa155ce5b782740ad0722722fa
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90169
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add support to configure DFSR table, introduce qupv3_clock_v2
structure to calculate register addresses for serial engines 2
and 3. Update CBCR registers to use the new structure for QUPv3
clock enablement.
BUG=b:444617760
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Dump DFSR registers for corresponding QUP and check if values are
updated properly into correct register address.
Change-Id: Ibd7e4bf121bd99130336047a50ed70d4cbec2234
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90145
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Toggle the RTC BUC control bit for Top Swap bootblock selection based on
the "attempt_slot_b" flag CMOS option, allowing to select which of the
BOOTBLOCK or TOP_SWAP regions to boot from.
This means that after an update, the CMOS option can be set to boot from
the newer TOP_SWAP bootblock. In case of failure, CMOS can be cleared to
revert to the known-good base BOOTBLOCK.
This is part of ongoing implementation of a redundancy feature proposed
on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Switching between identical bootblocks doesn't impact further boot flow,
i.e. selecting which FMAP region to load consecutive stages from.
That is to be enabled in following patches.
So far tested and enabled for the Alder Lake SoC.
TEST=Boot VP6650, setting the attempt_slot_b flag to different values,
observing that it resets/continues booting correctly.
Change-Id: Ib183a1f72ee8585b2c4ad4376344de33ff54cbb9
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
The recent increase of the RW size to 1756KB (CB:89545) has led to an
FMAP incompatibility. This issue arises during testing when both the ToT
firmware (which utilizes a new FMAP layout) and the firmware
branch-built firmware (which relies on an older FMAP layout) are used on
the same device.
To address this testing failure and streamline the testing process, the
updated FMAP will be exclusively implemented for the new variant. The
Navi and Hylia devices will continue to use the legacy FMAP.
BUG=b:461559917,b:463050048
TEST=emerge-{rauru,tanjiro} coreboot chromeos-bootimage
Change-Id: Icb4a12030f7a2e05757c903b70899c07b92c9875
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Add additional register configuration for the Realtek ALC257 audio
codec on the Lenovo ThinkPad T480. This includes:
- Hidden register SW reset sequence
- ClassD 2W amplifier configuration
- Jack detection (JD1) setup for headphone port
- Silence data mode threshold setting at -84dB
Shamelessly taken from google/brya/variants/pujjolo/hda_verb.c
Change-Id: Ib77138d782ceb9feeaef82935bc1c0d5c3066183
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Add driver to read 'hwid' file from CBFS and use it for SMBIOS product
name. Processes the ChromeOS-format HWID string by removing prefix
after colon, trimming whitespace, and extracting base name before
any hyphen/space. Returned string is normalized to have the first
character/letter capitalized, and the rest lower case. If no HWID file
is found in CBFS, the fallback is CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME.
This driver is intended to allow ChromeOS devices running upstream
coreboot to persist their board's unique HWID and use it as the SMBIOS
board name, but it is not limited to that function.
TEST=tested in MrChromebox downstream. Multiple devices which use the
same ChromeOS board but differ in HWID can use the same firmware image
and still be properly identified.
Change-Id: I1af1df4c79858d23ef71400abe72f41eec6c25c6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This is going to be used in some devices in place of KEY_ASSISTANT, map
it.
BUG=b:446676921
TEST=flashed and tested on a brox board, checked that the correct code
is generated with evtest
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I006c232c2924e8b6dc06338b0282c76f1f529a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90026
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looks like some devices may be using the capslock key, this a standard
code, just map it.
BUG=b:446677367
TEST=flashed and tested on a brox board, checked that the correct code
is generated with evtest
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: Ieb0f55e7f25a1b34d226efe12ad9dc481a53a082
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90025
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Chromium OS EC has some specialized handling of chromebook specific
function keys on the keyboard top row, these have a function specific
action key code that is exposed to the OS and used to map their
position, and also a specific scancode that has to be mapped to a Linux
event code.
This adds the necessary mapping for KEY_HOMEPAGE, which is going to be
used in new devices.
The scancode picked is 0xe012, which maps to e02a or 0xaa, the
corresponding EC CL is:
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/7118961
BUG=b:446007724
TEST=flashed and tested on a brox board with chromiumos, checked the
code with evtest
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I395721a342f507453dae19373df2f189ac1b5dac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90024
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
memory_info with dimm_info entries is available as CBMEM_ID_MEMINFO.
Moving the structures definitions to the commonlib allows the payloads
to easily access the memory information.
BUG=b:450374306
TEST=Build and boot Google/Brya
Change-Id: I25e788d5afd668e93f8ea60adaefb7b8b5d5ec28
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
To support Memory Tagging Extension (MTE), configure booker
(custom CI-700) registers related to MTE to set up MTE tag address.
According to CI-700 documentation, the por_mtu_tag_addr_base register is
only accessible by Secure accesses. Therefore these registers are now
configured in coreboot ramstage before passing to payloads.
BRANCH=rauru
BUG=b:438666196
TEST=manual test
Change-Id: I0d98cfee3e208a559116f84362528f005ea6f2c8
Signed-off-by: Jeff Xu <jeffxu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90141
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit updates the linker script to properly define and name the
DMA coherent memory regions used before and after DRAM initialization.
1. Rename Pre-RAM DMA Region:
The existing `DMA_COHERENT` region allocated in BSRAM at `0x14857000` is
renamed to `PRERAM_DMA_COHERENT`. This aligns the linker script with the
code changes (in `mmu.c`) which use the more specific name for the early
boot DMA buffer.
2. Add Post-RAM DMA Region:
A new region, `POSTRAM_DMA_COHERENT`, is defined at the very start of
DRAM (`0x80000000`) with an 8KB size. This region is intended for
general-purpose DMA operations that occur after DRAM is active,
ensuring a reserved, known, and uncached region for peripherals.
The memory map diagram comments are also updated to reflect these new
region names.
BUG=b:456953373
TEST=Able to build and boot google/quenbi.
Change-Id: I6fb4b9bf3425b311169ac43e1997f6574b571e00
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90098
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit relocates the following two regions:
1. `ddr_information`
2. `WATCHDOG_TOMBSTONE`
Previously, these regions were allocated in a higher address range
(starting near 0x14800000).
The regions are now defined within SSRAM`:
- `ddr_information` is moved from `0x14860000` to `0x146ABFE8`.
- `WATCHDOG_TOMBSTONE` is moved from `0x14818FFC` to `0x146ABFFC`.
This memory map change updates the linker script's visual diagram and
section definitions to reflect the new memory layout.
BUG=b:456953373
TEST=Able to build google/quenbi.
Change-Id: I4545722a836ec472e8086d1a941515cb3956c763
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90052
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MMU configuration in qc_mmu_dram_config_post_dram_init() needs to
include the memory region allocated for DMA coherent buffers.
Map the `postram_dma_coherent` region as UNCACHED_RAM to ensure memory
writes bypass the CPU cache hierarchy.
The mapping is only configured if the `_postram_dma_coherent` address
is different from `_preram_dma_coherent` address aka migration of the
region.
This is necessary for DMA operations that occur after DRAM is
initialized.
BUG=b:456953373
TEST=Able to build google/quenbi.
Change-Id: If5f625ad74f4f6ea244c8b377543be3666122cea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Refactor the DMA coherent memory region definition to support
stage-specific allocations.
In some boot flows, it is necessary to define separate DMA coherent
buffers for the early boot stage (e.g., romstage/bootblock) and the
later stage (ramstage). It allows the firmware to use only the memory
it needs, where it needs it, and prevents small-scale memory constraints
from crippling the overall boot flow.
The arch-specific, and now redundant, definitions of DMA_COHERENT are
removed from arm/memlayout.h and arm64/memlayout.h.
BUG=b:456953373
TEST=Able to build google/quenbi.
Change-Id: Ic32d14dda6cda0f731233dd3d86f3215c6af3637
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90049
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch relocates the coreboot stack from the BSRAM (Boot IMEM)
region to the SSRAM (Shared System RAM) region.
The 16K stack definition is moved from:
BSRAM region (0x14850000)
To:
SSRAM region (0x14680000)
This move is crucial because the BSRAM region is actively cleared during
the later stages of the IP loading process, which would wipe the stack
and lead to instability. Placing the stack in the persistent SSRAM
ensures it remains accessible throughout the early boot process.
BUG=BUG=b:456953373
TEST=Able to build google/quenbi w/ new stack region.
Change-Id: I59cd14fed2a5907bcbb8bed027dd5a55eb73e56d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90137
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add boot timestamps to measure the duration of loading the Secure OS
(BL32) payload in the `run_bl31()` function.
The Secure OS is loaded if the Kconfig option
`CONFIG_ARM64_USE_SECURE_OS` is enabled. The new timestamps are:
- "TS_TFA_LOAD_BL32_START": Placed immediately before the Secure OS
(BL32) loading process begins.
- "TS_TFA_LOAD_BL32_END": Placed after the BL32 entry point information
is set up and before the BL33 parameters are finalized.
This instrumentation helps profile the boot time cost of the Trusted
Firmware-A (TFA) BL32 component loading.
Change-Id: I6ca74b8d4b11dfab4829f8bc5fbaa39ee5212137
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Instrument the Qualcomm QCLib flow with timestamps to measure
execution time for both the initial loading/running phase and the
subsequent re-entry phase.
The timestamps are placed as follows:
- TS_QUALCOMM_QCLIB_INIT_START/END: Tracks the execution of
`qclib_load_and_run()`.
- TS_QUALCOMM_QCLIB_REINIT_START/END: Tracks the execution of
`qclib_rerun()`, which typically handles the AOP bring-up.
This instrumentation helps in profiling and optimizing the boot
performance on Qualcomm platforms.
Change-Id: I200ea5a78f4630000e80aed6dc38581af4d2e8aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90112
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch adds new timestamp IDs to track the execution flow within
the Qualcomm QCLib and the loading of the Secure OS (BL32) by the ARM
Trusted Firmware (TFA).
The following new IDs are introduced:
- TS_QUALCOMM_QCLIB_INIT_START (980)
- TS_QUALCOMM_QCLIB_INIT_END (981)
- TS_QUALCOMM_QCLIB_REINIT_START (982)
- TS_QUALCOMM_QCLIB_REINIT_END (983)
- TS_TFA_LOAD_BL32_START (998)
- TS_TFA_LOAD_BL32_END (999)
The reserved ID ranges are updated to accommodate these new vendor-
specific and architecture-specific timestamps:
- Intel/FSP range reduced from 950-989 to 950-980.
- A new range 980-990 is allocated for qualcomm/qclib.
- The Intel ME continued range is updated from 990-999 to 990-997.
- A new range 998-999 is allocated for ARM Trusted Firmware.
Change-Id: I904ac36862212a86961383dfe5e9b0f7ef0f02ea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90111
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
We used to put SMBIOS header and other data before VPD. That is not the
case anymore. New device will write the VPD starting at 0 instead of
0x600. Search VPD at 0x0 to support this.
TEST=build and boot google/geralt. VPD is found both at 0 and at 0x600.
Change-Id: I7072f7c646b6b55d11bc06dba5674828246fa1d0
Signed-off-by: Jian-Jia Su <jjsu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
S3 now works on Windows, so don't recommend switching to S0IX.
Change-Id: I5f5dac0f2bf5eddbfef041b12a134bb70fdd7577
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90125
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the datasheet and the LCD team’s response, increase Touch
IC enable delay time to resolve touch failure after resume.
BUG=b:458190286
TEST=1. Checked the touch screen power sequence waveform. The result is in b:458190286#comment4.
2. The touch feature works after resume.
Change-Id: Ia5a1d028721b1181d38730c23b27a80fa97e0dd7
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Due to project requirements, GPP_D16 and GPP_D17 are not used. This has been confirmed by both the schematic and the LCFC hardware engineers. Therefore, they should be removed from the fw_config.
schematics: RUBY_EVT_0902_2112.pdf
BUG=b:452216678
TEST=Build FW and boot to OS, check DMIC function works.
Change-Id: I195ad082836d3b8a4fa79cbbc9e4bffaec745011
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90071
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
