memlayout: Introduce PRERAM and POSTRAM DMA coherent regions
Refactor the DMA coherent memory region definition to support stage-specific allocations. In some boot flows, it is necessary to define separate DMA coherent buffers for the early boot stage (e.g., romstage/bootblock) and the later stage (ramstage). It allows the firmware to use only the memory it needs, where it needs it, and prevents small-scale memory constraints from crippling the overall boot flow. The arch-specific, and now redundant, definitions of DMA_COHERENT are removed from arm/memlayout.h and arm64/memlayout.h. BUG=b:456953373 TEST=Able to build google/quenbi. Change-Id: Ic32d14dda6cda0f731233dd3d86f3215c6af3637 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90049 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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4 changed files with 28 additions and 10 deletions
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@ -22,11 +22,6 @@
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REGION(stack, addr, size, 8) \
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_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.mk");
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#define DMA_COHERENT(addr, size) \
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REGION(dma_coherent, addr, size, SUPERPAGE_SIZE) \
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_ = ASSERT(size % SUPERPAGE_SIZE == 0, \
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"DMA coherency buffer must fit exactly in full superpages!");
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#define FRAMEBUFFER(addr, size) \
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REGION(framebuffer, addr, size, SUPERPAGE_SIZE) \
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_ = ASSERT(size % SUPERPAGE_SIZE == 0, \
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@ -9,11 +9,6 @@
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REGION(ttb, addr, size, 4K) \
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_ = ASSERT(size % 4K == 0, "TTB size must be divisible by 4K!");
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#define DMA_COHERENT(addr, size) \
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REGION(dma_coherent, addr, size, 4K) \
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_ = ASSERT(size % 4K == 0, \
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"DMA buffer should be multiple of smallest page size (4K)!");
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#define FRAMEBUFFER(addr, size) \
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REGION(framebuffer, addr, size, 1M) \
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_ = ASSERT(size % 1M == 0, \
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@ -101,6 +101,32 @@
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ALIAS_REGION(postram_cbfs_cache, cbfs_cache)
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#endif
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/* Use either DMA_COHERENT (unified) or both (PRERAM|POSTRAM)_DMA_COHERENT */
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#define DMA_COHERENT(addr, size) \
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REGION(dma_coherent, addr, size, 4K) \
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_ = ASSERT(size % 4K == 0, \
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"DMA buffer should be multiple of smallest page size (4K)!"); \
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ALIAS_REGION(dma_coherent, preram_dma_coherent) \
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ALIAS_REGION(dma_coherent, postram_dma_coherent)
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#if ENV_ROMSTAGE_OR_BEFORE
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#define PRERAM_DMA_COHERENT(addr, size) \
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REGION(preram_dma_coherent, addr, size, 4K) \
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_ = ASSERT(size % 4K == 0, \
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"Pre-RAM DMA buffer should be multiple of smallest page size (4K)!"); \
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ALIAS_REGION(preram_dma_coherent, dma_coherent)
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#define POSTRAM_DMA_COHERENT(addr, size) \
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REGION(postram_dma_coherent, addr, size, 4K)
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#else
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#define PRERAM_DMA_COHERENT(addr, size) \
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REGION(preram_dma_coherent, addr, size, 4K)
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#define POSTRAM_DMA_COHERENT(addr, size) \
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REGION(postram_dma_coherent, addr, size, 4K) \
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_ = ASSERT(size % 4K == 0, \
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"Post-RAM DMA buffer should be multiple of smallest page size (4K)!"); \
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ALIAS_REGION(postram_dma_coherent, dma_coherent)
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#endif
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/* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
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#if ENV_DECOMPRESSOR
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#define DECOMPRESSOR(addr, sz) \
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@ -73,6 +73,8 @@ DECLARE_REGION(ramstage)
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DECLARE_REGION(pagetables)
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DECLARE_REGION(ttb)
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DECLARE_OPTIONAL_REGION(ttb_subtables)
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DECLARE_OPTIONAL_REGION(preram_dma_coherent)
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DECLARE_OPTIONAL_REGION(postram_dma_coherent)
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DECLARE_REGION(dma_coherent)
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DECLARE_REGION(soc_registers)
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DECLARE_OPTIONAL_REGION(framebuffer)
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