memlayout: Introduce PRERAM and POSTRAM DMA coherent regions

Refactor the DMA coherent memory region definition to support
stage-specific allocations.

In some boot flows, it is necessary to define separate DMA coherent
buffers for the early boot stage (e.g., romstage/bootblock) and the
later stage (ramstage). It allows the firmware to use only the memory
it needs, where it needs it, and prevents small-scale memory constraints
from crippling the overall boot flow.

The arch-specific, and now redundant, definitions of DMA_COHERENT are
removed from arm/memlayout.h and arm64/memlayout.h.

BUG=b:456953373
TEST=Able to build google/quenbi.

Change-Id: Ic32d14dda6cda0f731233dd3d86f3215c6af3637
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90049
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2025-11-18 08:30:34 +00:00 committed by Matt DeVillier
commit 931fa9c01d
4 changed files with 28 additions and 10 deletions

View file

@ -22,11 +22,6 @@
REGION(stack, addr, size, 8) \
_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.mk");
#define DMA_COHERENT(addr, size) \
REGION(dma_coherent, addr, size, SUPERPAGE_SIZE) \
_ = ASSERT(size % SUPERPAGE_SIZE == 0, \
"DMA coherency buffer must fit exactly in full superpages!");
#define FRAMEBUFFER(addr, size) \
REGION(framebuffer, addr, size, SUPERPAGE_SIZE) \
_ = ASSERT(size % SUPERPAGE_SIZE == 0, \

View file

@ -9,11 +9,6 @@
REGION(ttb, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, "TTB size must be divisible by 4K!");
#define DMA_COHERENT(addr, size) \
REGION(dma_coherent, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, \
"DMA buffer should be multiple of smallest page size (4K)!");
#define FRAMEBUFFER(addr, size) \
REGION(framebuffer, addr, size, 1M) \
_ = ASSERT(size % 1M == 0, \

View file

@ -101,6 +101,32 @@
ALIAS_REGION(postram_cbfs_cache, cbfs_cache)
#endif
/* Use either DMA_COHERENT (unified) or both (PRERAM|POSTRAM)_DMA_COHERENT */
#define DMA_COHERENT(addr, size) \
REGION(dma_coherent, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, \
"DMA buffer should be multiple of smallest page size (4K)!"); \
ALIAS_REGION(dma_coherent, preram_dma_coherent) \
ALIAS_REGION(dma_coherent, postram_dma_coherent)
#if ENV_ROMSTAGE_OR_BEFORE
#define PRERAM_DMA_COHERENT(addr, size) \
REGION(preram_dma_coherent, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, \
"Pre-RAM DMA buffer should be multiple of smallest page size (4K)!"); \
ALIAS_REGION(preram_dma_coherent, dma_coherent)
#define POSTRAM_DMA_COHERENT(addr, size) \
REGION(postram_dma_coherent, addr, size, 4K)
#else
#define PRERAM_DMA_COHERENT(addr, size) \
REGION(preram_dma_coherent, addr, size, 4K)
#define POSTRAM_DMA_COHERENT(addr, size) \
REGION(postram_dma_coherent, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, \
"Post-RAM DMA buffer should be multiple of smallest page size (4K)!"); \
ALIAS_REGION(postram_dma_coherent, dma_coherent)
#endif
/* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
#if ENV_DECOMPRESSOR
#define DECOMPRESSOR(addr, sz) \

View file

@ -73,6 +73,8 @@ DECLARE_REGION(ramstage)
DECLARE_REGION(pagetables)
DECLARE_REGION(ttb)
DECLARE_OPTIONAL_REGION(ttb_subtables)
DECLARE_OPTIONAL_REGION(preram_dma_coherent)
DECLARE_OPTIONAL_REGION(postram_dma_coherent)
DECLARE_REGION(dma_coherent)
DECLARE_REGION(soc_registers)
DECLARE_OPTIONAL_REGION(framebuffer)