Starting with Lunar Lake, the scaling factor information is
centralized in the power control unit (PCU) firmware. In order to keep
all firmware in sync, it is recommended to read the scaling factors
from the PCU firmware instead of using hard-coded values.
This commit adds a new Kconfig option,
CONFIG_SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS, to allow
SoC specific code to specify its own function to read the core scaling
factors.
When this option is enabled, the soc_read_core_scaling_factors()
function from the SoC specific code is used to read the core scaling
factors instead of using the statically defined values
CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR and
CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR.
Change-Id: Icdf47e17cc5a6d042f3c5f90cf811fccd6c1ed9b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85553
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a module_id field to the cpu_topology structure.
This field is used to identify the module that a CPU is located
on. This information is useful for power management and other
purposes.
Change-Id: I1c8a76dce48c0539a3f36015674553a2461dec27
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85577
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This silences a few warnings in FSP.
Change-Id: I3bef919d1c6fcb9abff4fc49300321c9d471cb82
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This reverts commit 9e3f614598.
This is used for S3, so keep it in the devicetree.
Change-Id: If69bb946d31e842af9caf84470ddd32900e56456
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add an option to set the Power LED to a lower brightness level
Change-Id: I39507d4f2e572ca31ad982ce0d730a0d00f6ca32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85702
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the reset delay to 300ms from 10ms according to the
datasheet.
Change-Id: I8e608347efec03b408a5f44c4f8f2221855e2532
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set the Touch Panel Reset (GPP_F17) to host owned so that it
can be controlled by the OS via ACPI.
Change-Id: I3e1249addcfb831deee81024a37a867c79b1b0f9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
For the boards that use Intel PTT, select TPM2 so
that the physical presence interface is generated in
the SSDT.
Change-Id: I4d6633291ba635c5a2f7eb36e64a327d9a4da5cf
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add entries to the SSDT so that the volume keys, which
use the PS2 keyboard interface, are correctly registered.
Change-Id: Ie80491559de50d72bf1ff97fd30c1a74e6b0f7a6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85695
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust these so they simply adjust the Intel detaults, rather than
having hardcoded values.
Change-Id: I8375428e9ace8e505e8cb53b2e4912592715b79a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85694
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This seems to make no noticeable difference, but configure
these interfaces according to the schematics. Enable HPD
for all DisplayPort links and DDC for HDMI links.
Change-Id: I0f736761bcc177afebb98eb2f612b089bc6f13a4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Adjust ACPI so they are consistant across all boards.
Change-Id: If0fd6b3dd67583842e4520679b7a9c3ab9f433c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
FSP defaults to using pins that are used for LPC; given that
coreboot and these boards only supports eSPI, set these pins
accordingly.
If this is not done, FSP will assert and not boot.
Change-Id: Ide4d92211fa7ab496c38ce1c4e895337c269d247
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Use the newly created Intel Bluetooth ACPI driver.
Change-Id: I6438a21a73e8ddab21fb5b9021fb4d5e2f8c1c22
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84636
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The default i2c speed is I2C_SPEED_STANDARD, but the coreboot
driver defaults to I2C_SPEED_FAST.
The difference in performance and power consumption is
negligible, so set the buses to fast and remove the
superfluous option.
Change-Id: Ic722e971e6f94965d28fd158a46d144a19490199
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Ensure any reads or writes to the EC memory, are performed with ECRD
(Read) and ECWR (Write) as these methods use a mutex.
Also, use local variables to cache reads of the same variable within
a given ACPI method.
This solves:
Initialized Arguments for Method [ECRD]: (1 arguments defined for method invocation)
Arg0: 00000000967261a4 [RefOf] <Node> Name ECPS RegionField 000000007d4b8073
ACPI Error: Aborting method \_SB.PCI0.LPCB.EC.ECRD due to previous error (AE_BAD_PARAMETER) (20230628/psparse-529)
ACPI Error: Aborting method \_SB.PCI0.LPCB.EC.ADP1._PSR due to previous error (AE_BAD_PARAMETER) (20230628/psparse-529)
Change-Id: I0bbb538017cc004bff1989a8017ccfcd1ba9ab5c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84734
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These GPIOs are required for the two Thunderbolt ports to
function correctly, enable them.
Change-Id: Id3f42b28258424d713325b19e317583494111577
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This platform uses eSPI so these are not used; disable them.
Change-Id: Ied0ffb2999ef0582570b94d756c2fcbd131b7ccf
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84732
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This GPIO isn't connected to anything so remove the config.
Change-Id: I8792a28877dc180eeb44386fefff15b3f75f4699
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add additional configuration to the RDT3 to improve power saving.
The savings range from 0.05W to 0.2W depending on the device.
Tested on all devices, with Ubuntu 24.04 by verifying general
functionality of the connected device.
Change-Id: Ibb34e1c16b110cc1478c7bdb8d1b4c0d4ebc11c9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Explicitly set ASPM and L1 Substates to maximum, to avoid instances
where the default "AUTO" in FSP will fail to detect the highest
level.
Tested on all devices, with Ubuntu 24.04 by verifying general
functionality of the connected device.
Change-Id: I9f156124925bebd8588d863661bb2702c552f657
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84727
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Include `default_brightness_levels.asl` in the DSDT, and
add the default brightness levels entry to the igpu.
This allows brightness controls to be used on Windows.
Change-Id: Ide0bec650e010fd294b852f640b275df6f939393
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The memory used in the StarLite Mk V supports 5500MT/s through 7500MT/s.
Intel recommends 5500MT/s for stability, but let the user make up their
own mind.
Change-Id: Ie77d3be122478d5e674f92f8085930ae38ff2de1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Allow boards that use the merlin EC to disable the lid switch.
Change-Id: Ib5f71ce46e9e97a1a02e4ea5af6aeb094ee6fad7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84634
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow boards that use the merlin EC to configure the charging speed,
as all versions of the merlin EC support this.
All coreboot does it write a value to the EC RAM and the EC will
handle the rest.
Change-Id: I46faa540530c5bd7f5473021561380213158152e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 50b7976bb2 ("ec/starlabs/merlin: Remove ITE mirror
functionality") removed the mirror_flag param from the EC code, but
some remnants were left behind in the platform and mainboard code.
Drop these unused bits.
TEST=build/boot starlabs/starlite_adl
Change-Id: I6eb8c9a6ef8f92e2d92081b8451cef8d7246ff7e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Fix the typo in the word "unknown", and add 1 to the timepoint enum to
print out 1, 2 and 3 instead of 0, 1 and 2.
Change-Id: I1308fd102490a89ff8b724509917180034d8d0c0
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
GPUEB is a micro-processor used for GPU power management. It is also
responsible for controlling GPU DVFS and GPU thermal throttling. This
gpueb load flow adds 47ms to the boot time.
coreboot log:
CBFS: Found 'gpueb_fw.img' @0x84740 size 0x29736 in mcache @0xfffdd374
Loaded (and reset) gpueb_fw.img in 47 msecs.
TEST=Boot ok
BUG=b:317009620
Signed-off-by: Andy.Hsu <andy.hsu@mediatek.corp-partner.google.com>
Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Configure ALC5650 for Hylia to support beep sound in the payload.
BRANCH=rauru
BUG=b:383376419
TEST=Verify devbeep in depthcharge console
Change-Id: I2c247be87ad212fa52e21e1e6da17c07d82f1988
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85858
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Disabling RAPL via Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS does
not turn off RAPL completely (i.d. MMIO & MSR).
In the past it was assumed disabling RAPL via MCHBAR is sufficient and
the corresponding changes are also reflected in the related
MSR (0x610-PACKAGE_POWER_LIMIT). This is not the case for
Power Limit 2 (PL2) because Bit[47]-PKG_PWR_LIM_2_EN is still set
although PL1 and PL2 were disabled through MCHBAR.
Thus Bit[10]-POWER_LIMITATION_STATUS flag can be set in
MSR 0x19C (THERM_STATUS) when the power limit of the SKU exceeds.
This may lead to a throttling of the domain level frequency.
Moreover related parameters within the same
MSR (0x610-PACKAGE_POWER_LIMIT) like PKG_PWR_LIM_TIME, PKG_CLMP_LIM,
PKG_PWR_LIM have to be cleared as well for both Power Limits
(PL1 & PL2). This is due to the fact that these parameters stray in to
the system and may effect different system settings.
With this commit the PACKAGE_POWER_LIMIT MSR is cleared additionally to
the MCHBAR setting when build for ElkhartLake.
TEST=Verify MSR(0x610-PACKAGE_POWER_LIMIT) is set to zero during OS
runtime except Bit[15]-PKG_PWR_LIM_1_EN (it is known as a bug that this
bit will be set to 1 anyway).
Moreover using a system stress test tool (e.g. Passmark's BurnInTest)
and stressing the system hard should not lead to
Bit[10]-POWER_LIMITATION_STATUS flag being set. This is the case when
MSR (0x610-PACKAGE_POWER_LIMIT) is not cleared completely and the
system is stressed intensively.
Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85606
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since commit 34a7e66faa ("util/cbfstool: Add a new mechanism to
provide a memory map") the ext-win-base and ext-win-size option has been
replaced with the "--mmap" option.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I33cfb59d9dbe88c4f618301ac1506e3281b1a483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
- Add step for building ifdtool (might not be obvious)
- Remove "./ifdtool COREBOOT_NAME" because it does nothing
- Add a small comment explaining what the -d and -x args do.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I868ea8918a1566cfade3bc161117f2ca8dfed31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85235
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The fsp_params.c file is refactored to move the debug message
control logic to a separate function, fsp_control_log_level().
This function takes an FSPM_UPD pointer and a boolean value
indicating whether debug messages should be enabled or disabled.
The fill_fsp_event_handler() function is updated to call
fsp_control_log_level() with the appropriate boolean value based on
the CONFIG(CONSOLE_SERIAL) and CONFIG(FSP_ENABLE_SERIAL_DEBUG)
Kconfig options.
BUG=b:227151510
TEST=Able to build and boot google/fatcat.
Change-Id: Ie2916ce82133058464d20eed327de7c7288e78a4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85827
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit renames the Meteor lake Touch Controller device IDs to
include the supported bus/protocol for clarity. The IDs comes from
document #640228 - Meteor Lake External Design Specification volume 1.
Change-Id: I60d9bec60d0578bd5a12a4df25248b7ae58539d6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85644
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This isn't used anywhere, so remove it.
Change-Id: Ieb5980929ef35ae129f9e548da7ab71efa2ae7f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84594
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ASPM helper functions are the same for all Intel SOCs
since Skylake, so move them to common code.
Change-Id: Ic6876e920d75abbbbb27d4ce3a4f2c08a8db9410
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83679
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
BUG=b:387056119
BRANCH=none
TEST=built firmware and verified by power team, and noise pass.
Change-Id: I11e1fae6d0b8508760090956ca6d77b012aa4bad
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85826
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Based on discussions on various patches (CB:57140), the idea was to
enable all bits to avoid incomplete ports.
Therefore, enable all bits - the same as ADL.
Change-Id: I5ace878faa09b959384338efcdbdfce390145002
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add a null check around the usage of the RFWU (Retimer Firmware
Update path) in the `usb4_retimer_execute_ec_cmd` function. This
ensures that any interaction with RFWU is only performed when the
path is valid, preventing potential null pointer dereferences.
This fixes are large amount of errors when `ec_retimer_fw_update_path`
isn't declared, such as comparisons like `If ((Local0 == Break))`.
Change-Id: I5a219345440f91332f680885b51e2cc09f14f7a7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
The current Pull-Down capabilities of the SPMI are insufficient and
require optimization. Configure the SCL and SDA of the SPMI-P to
Pull-Down mode on MT8196 SoC side. It is done only once during the SPMI
read check to fix SPMI clock calibration failure.
TEST=Build pass
BUG=b:361174333
Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85751
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8
"Other Device ID" specifies that the first Thunderbolt PCIe root port
number is 21.
The previous offset of 0x10, inherited from Meteor Lake code, caused
an issue that resulted in:
- Temporary deactivation of Thunderbolt PCI devices during ramstage
- Failure to generate critical ACPI SSDT power management data for the
port
This error led to instability in PCIe tunneling during power state
transitions.
Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85781
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since all USB configurations are read from the southbridge devicetree,
these configurations aren't used anymore.
TEST=Built Z220 CMT with BUILD_TIMELESS=1, output ROMs are identical.
Change-Id: I8f478625ad4928cf23bbb8ac2689004010bbdd4b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85817
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
There are several unused includes here.
TEST=Built 8200 usdt with BUILD_TIMELESS=1, no change in output ROM.
Change-Id: Ib4082a2589441b1d257db622380733e2825b27c2
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This change adds support for the generic LPC memory range configuration
in the EC ACPI code.
If CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled, the
EC will use the generic LPC memory range for EMEM related communication
between EC and AP Firmware. This is useful for platforms that do not
have a dedicated IO range like accessed EMEM through port 62/66 or
through LPC at 900h.
The generic LPC memory range is defined by the _SB.PCI0.LPCB.GLGM()
method. This method returns the base address and size of the memory
range.
Update the comment section to reflect the alternative source for EMEM
data when CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled.
BUG=b:354066052
TEST=Build and boot on a device with
CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE enabled.
Change-Id: I8038e2827ec7e301bad3a5a58df007f3a448bad7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
To improve boot time, raise little CPU from 700MHz to 2.4GHz at romstage
(before DRAM calibration).
FW logs:
Check CPU freq: 2400120 KHz
BUG=b:317009620
TEST=Build pass, boot ok.
Change-Id: I14a31f3a51ca246b842cc0ef740c43ff5d857310
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
