This change adds the wake source for the touchpad on the
google/fatcat mainboard.
This allows the touchpad to wake the system from suspend.
BUG=b:274919134
TEST=Verified that the system can be woken up from suspend by tapping
the touchpad.
Change-Id: I6b265fb6b220cc779ea011e767ae98d4cf37e0d2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This change modifies the touchpad interrupt configuration to use
edge-triggered interrupts instead of level-triggered interrupts.
This is necessary to ensure that the touchpad interrupt is properly
detected by the AP w/o seeing interrupt flood.
BUG=b:376019577
TEST=Verified that the touchpad works smoothly with this change.
Change-Id: Ida0dfe10963a979c5e977133149d97799a76e3b3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85802
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow the power team’s recommendation:
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8
- Set FastPkgCRampDisable VCCIA and VCCGT to "true"
BUG=b:380384127
TEST=built firmware and verified by power team, and noise pass
Change-Id: Ib7f60f1248c6b46f4f9bac1731be4f0396766ae2
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85798
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
has_power_resource is a boolean, so use true, false instead of 0, 1.
Change-Id: I25b86ef577e072cfe3ef5dc2447113f11c51f747
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Modify early pad configuration TPM bus from I2C3 to I2C1.
Francka TPM bus is I2C1.
BUG=b:377819511
TEST=emerge-fatcat coreboot
Change-Id: Id08575d28f6f3bced74c0b301756fc8239cfd190
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85736
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In MT8196, CKSYS achieves power efficiency by dynamically turning the
clocks on or off based on the status provided by PERI.
TEST=Build pass, boot log:
mtk_cksys_init = 0x1
BUG=b:317009620
Change-Id: I70f710f068d7d882037691930a90c83adaab15d2
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The plan is to have a setup menu in edk2 to configure coreboot options
without having to describe the options in both coreboot and edk2; that
would be a maintenance nightmare. Options are passed to edk2 using CFR
structures, edk2 stores the values in the variable store in flash, and
coreboot reads the option values using the EFI variable store backend.
Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Fix some typos and also update the naming convention of
`CFR_OPTFLAG_GRAYOUT` to `CFR_OPTFLAG_INACTIVE` as per reviews.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Id66808382b93e32c58024462c18b20c2a89d6d23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Change the ram_id to 2 for MT62F2G32D4DS-020 WT:F based on the
hardware schematic MB_SCH_1224A.
BUG=b:372395010
TEST=Run part_id_gen tool and check the generated files.
Change-Id: Ia486d892fca0ed2a9e3e869b97b43af617ef17ac
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85775
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ensure the board can boot by limiting the power limits if the battery
is missing. This addresses the factory use case.
BUG=b:377798581
TEST=See power limit override log message when the battery is missing
on fatcat board
Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85146
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces a new function,
google_chromeec_is_barrel_charger_present(), which checks if a barrel
charger is present.
The function uses the following logic to determine if a barrel charger
is present:
- If both a barrel charger and USB-C PD are present, then the barrel
charger takes precedence over USB-C PD. As a result,
google_chromeec_is_usb_pd_attached() will return false. This logic can
be used to deterministically say if a barrel charger is present even
when both a barrel charger and USB-C PD are attached.
- If an AC charger is detected and USB-C PD is not present, then a
barrel charger must be present.
This change allows the EC to accurately detect the presence of a barrel
charger, even when a USB-C PD charger is also attached.
BUG=b:377798581
TEST=Able to read the charger status correctly while booting
google/fatcat.
Experiment #1:
- USB-C PD Attached = yes
- Barrel Attached = No
- Charger Detected = Yes
```
fatcat-rev257 ~ # cbmem -c | grep -5 "ac_charger_present"
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: yes
[INFO ] baseboard_devtree_update: Barrel Absent
```
Experiment #2:
- USB-C PD Attached = No
- Barrel Attached = Yes
- Charger Detected = Yes
```
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Present
```
Experiment #3:
- USB-C PD Attached = Yes
- Barrel Attached = Yes
- Charger Detected = Yes
```
[INFO ] ac_charger_present: yes
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Present
```
Experiment #4:
- USB-C PD Attached = No
- Barrel Attached = No
- Charger Detected = No
```
[INFO ] ac_charger_present: no
[INFO ] usb_pd_present: no
[INFO ] baseboard_devtree_update: Barrel Absent
```
Change-Id: I9644f0dec057f95bb0a22cdc18edc1a0234ee3a9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch adds a new API `google_chromeec_is_below_critical_threshold()
` to check if the battery level is below the critical threshold.
The API uses the existing `ec_cmd_battery_get_dynamic()` command to
retrieve the battery flags and checks the `EC_BATT_FLAG_LEVEL_CRITICAL`
flag to determine if the battery level is critical.
This API can be used by other components to query the battery critical
status and take necessary actions, for example, while the system is
booting with low battery fuel with and/or without an AC
charger attached.
This addresses the need to implement a low battery charger icon and
detect when the system is booting with low battery fuel. The existing
`google_chromeec_is_battery_present_and_above_critical_threshold()`
API is not suitable for this purpose because any negative decision
(like battery not present and/or battery is critically low) implemented
around this existing API will also render the lower battery indicator
when the system is booting into battery cut-off mode. Ideally, we do not
wish to render any icon and simply allow boot to the OS during system
battery cut-off boot.
BUG=b:377798581
TEST=Able to read the battery status correctly while booting
google/fatcat.
Change-Id: Id1fc1df374fb4c663becc371c69b285d8b9957ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85759
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch introduces a new API, `google_chromeec_is_charger_present()`,
to determine if a charger is connected.
The API leverages the existing `ec_cmd_battery_get_dynamic()` command
to retrieve battery flags and checks the `EC_BATT_FLAG_AC_PRESENT`
flag to ascertain charger presence.
Other components can leverage this API to query the charger status,
which is particularly useful for distinguishing between barrel chargers
and USB-C chargers after relying on the
`google_chromeec_is_usb_pd_attached()` API.
BUG=b:377798581
TEST=Able to read the charger status (w/ barrel and/or w/ USB-PD)
correctly while booting google/fatcat.
Change-Id: Iadf81400f71a51c093f71fe995cacc107c50c7af
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85758
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change introduces a new API, `google_chromeec_is_usb_pd_attached()`
which checks the current status of the USB-C port and returns whether a
USB Power Delivery (PD) charger is currently connected.
This API is useful for determining if the system is currently being
powered by a PD charger.
BUG=b:377798581
TEST=Able to read the PD status correctly while booting google/fatcat.
Change-Id: I47c934ee8a7563d4ba5124bff5613e61dd66e923
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add MT6685 initial settings and ADC init settings to support Thermal
Information Acquisition (TIA). TIA will read thermal info in HW.
TEST=Build pass
BUG=b:317009620
Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85734
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Use the helper functions added to Alder Lake which will configure
ASPM and L1 Subsstate control based on Kconfig, but retain the
capability to override the specific levels from devicetree.
Change-Id: Ia5cc11188b245a93c303117589bd9d3c18c2877e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83678
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As Intel has provided fixes regarding CLKREQ pins issue with new
UPD settings as described in commit b8abde7a8e
("soc/intel/alderlake: Disable PCIe clock gating"), remove this
WA as introduced by this commit 586b1c8da0
("mb/prodrive/atlas: Add workaround for CLKREQ pins").
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Icbab617428551accda66499b7c2a32b2fa8c1689
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79021
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the interrupt GPIO for LPSS I2C based touchpad from GPP_F18
to GPP_A13 to match the current fatcat configuration.
BUG=b:376019577
TEST=Able to verify the touchpad functionality using 'THAT' touchpad
module.
Change-Id: I37a9d3aae67883f9eb4f47d76b4f48ac6ebb6d16
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85754
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Fix regression introduced in commit 177bb5e9b9
("soc/intel/xeon_sp: Revise IIO domain ACPI name encoding").
Ensure domain ACPI names in the DSDT are in sync with SSDT ACPI names.
Fixes PCI devices not discovered on socket 1-3.
TEST: Booted in ibm/sbp1 and found all PCI devices working, no errors
in dmesg are shown.
Change-Id: Ice168bdebc46dc0cfb9c63c78c46a5d9ff2b7658
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Disable stylus function based on hardware schematic diagram.Because the external environment is floating, EE requires setting GPIO output to be pulled high or low.
BUG=b:372506691
TEST=Local build successfully.
Change-Id: I7b72284ab173633405d5de9541f0ea7520d09658
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85738
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Those documents have been moved to the archive.
Previous URLs now point to the documentation hub.
Change-Id: Ibb478b56d02842dc05475235b0fe80ab6c4e7d04
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The MFGPLL_*_BASE addresses are based on MFGSYS_BASE (0x40000000)
instead of IO_PHYS (0x10000000). Rewrite the address calculation for
readability.
Also rename these macros to MFG_PLL_* to make them consistent with other
macros to be added in CB:85654.
Change-Id: Ifd5d77b95c698cb6030c58ba259f2cdf2a29d87b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85740
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Retrieve the SKU ID for Rauru via CBI interface. If that failed
(or no data found), fall back to ADC channels for SKU ID.
TEST=Build pass, boot ok, log show:
SKU Code: 0x2
BUG=b:317009620
Change-Id: I49ba6f428f55d3aae1b84a4d5ce06bec765caece
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85666
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
We add storage_id() to read the storage id from auxadc.
BUG=b:317009620
TEST=Build pass
Change-Id: I036df324cd6644ff69110c6247af29360b83225f
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85717
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add pujjo new supported memory parts in mem_parts_used.txt.
Generate SPD id for this part.
Hynix H58G56CK8BX146
BUG=b:385659484
TEST=Use part_id_gen to generate related settings
Change-Id: Idb48e849424aac79ef9af29f21b84194455c813e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85735
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
These files were originally from MediaTek and follow coreboot's main
license: "GPL-2.0-only". Now MediaTek replaces this file to
"GPL-2.0-only OR MIT" license for better code re-use in other open
source software stack.
BUG=b:379008996
BRANCH=none
TEST=build pass
Change-Id: I2821a8c097b8d22e1aa91b316ae0fdce80f342de
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85723
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch enhances the readability of the CSE sync event
ELOG_TYPE_FW_CSE_SYNC by updating the event naming from "early and late
bootstage" to "pre and post memory."
BUG=b:379585294
TEST=boot verified on google/rex0 and google/rex64
without change:
```
rex-rev3 ~ # elogtool list
rex64-rev3 ~ # /media/usb/elogtool list
3 | 2024-01-01 22:25:59-0800 | Firmware CSE sync | Late CSE Sync
```
with change:
```
rex64-rev3 ~ # elogtool list
3 | 2024-12-17 02:22:36-0800 | Firmware CSE sync | Post RAM CSE Sync
```
Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Adjust the EC memory map range for indexed IO access in trulo variant
from 0x900 to 0x380
BUG=b:379224648
TEST= able to build nissa/trulo.
Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85547
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for indexed IO for ec communication, Indexed I/O allows
memory access using a single I/O port base address usually called an
index register and another port address called a data register.
BUG=b:379224648
TEST= able to build nissa/trulo.
Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch creates a new quandiso2 variant which is a Twin Lake
platform. This variant uses Quandiso board mounted with the Twin Lake
SOC and hence the plan is to reuse the existing quandiso code.
BRANCH=firmware-nissa-15217.B
TEST=build, and boot into OS
Change-Id: I404b579f1758c637d3456f6bed7119e3f4ecc06c
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85570
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Depending on the environment, the /data-in directory might be owned by
root and recent git versions refuse to work in these. So explicitly
mark /data-in as a safe environment.
Change-Id: Ia534928f759e50c2dfb1df8af653dee74c734603
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
There is no reason to stick to the point releases. So use the 3.19 base
image referring to the latest minor release instead. Also, update
installed packages to latest versions from that release.
Change-Id: Ic947f99ae7231918ec2e6105f8f3050a17fd1176
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
It seems the .bashrc is not loaded as intended and thus the bash
mechanisms never worked. So drop the bash invocations and replace them
with the ash shell. Also, don't modify the PATH variable since this is
done by the activation script.
Change-Id: I544a15c86c212e91ece59b583fb61dad37fca337
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Volumes are mounted with the command line parameter. Using the VOLUME
directive creates a persistent storage in a standard path, which is not
intended. So drop that and create equal directories in order to keep the
container working.
Change-Id: I9b3551cca34d846aba5ca5c89162f82baa6de768
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85724
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
