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mb/starlabs/*: Enhance RTD3 configuration

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Add additional configuration to the RDT3 to improve power saving.
The savings range from 0.05W to 0.2W depending on the device.

Tested on all devices, with Ubuntu 24.04 by verifying general
functionality of the connected device.

Change-Id: Ibb34e1c16b110cc1478c7bdb8d1b4c0d4ebc11c9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2024-10-11 11:58:09 +01:00
commit efa9b62a48
6 changed files with 189 additions and 134 deletions
Download patch file Download diff file Expand all files Collapse all files

65
src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
View file

@ -138,47 +138,52 @@ chip soc/intel/alderlake
end
device ref pcie_rp9 on # RLT8111 (LAN 1)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen4x1"
"SlotLengthShort"
"SlotTypePci"
"SlotDataBusWidth4X"
smbios_slot_desc "SlotTypePciExpressGen4x1"
"SlotLengthShort"
"SlotTypePci"
"SlotDataBusWidth4X"
end
device ref pcie_rp10 on # RLT8125B (LAN 2)
register "pch_pcie_rp[PCH_RP(10)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X4"
"SlotLengthShort"
"SlotTypePci"
"SlotDataBusWidth4X"
smbios_slot_desc "SlotTypePciExpressGen3X4"
"SlotLengthShort"
"SlotTypePci"
"SlotDataBusWidth4X"
end
device ref pcie_rp12 on # SSD x4
register "pch_pcie_rp[PCH_RP(12)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X4"
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
smbios_slot_desc "SlotTypePciExpressGen3X4"
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
register "srcclk_pin" = "0"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
register "srcclk_pin" = "0"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
device generic 0 on end
end
end

61
src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
View file

@ -136,45 +136,54 @@ chip soc/intel/alderlake
end
device ref pcie_rp5 on # WiFi
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
"M.2/M 2230"
"SlotDataBusWidth1X"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
"M.2/M 2230"
"SlotDataBusWidth1X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
register "srcclk_pin" = "2"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
register "srcclk_pin" = "2"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
device generic 0 on end
end
end
device ref pcie_rp9 on # SSD x4
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_detect_timeout_ms = 50,
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_detect_timeout_ms = 50,
}"
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
register "srcclk_pin" = "1"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
register "srcclk_pin" = "1"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
device generic 0 on end
end
end

67
src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
View file

@ -23,30 +23,35 @@ chip soc/intel/alderlake
# Device Tree
device domain 0 on
device ref igpu on
register "gfx" = "GMA_DEFAULT_PANEL(0)"
register "ddi_portA_config" = "1"
register "gfx" = "GMA_DEFAULT_PANEL(0)"
register "ddi_portA_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
end
device ref pcie4_0 on # SSD x4
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)"
register "srcclk_pin" = "4"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)"
register "srcclk_pin" = "4"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
device generic 0 on end
end
end
@ -168,24 +173,28 @@ chip soc/intel/alderlake
device ref shared_sram on end
device ref pcie_rp5 on # WiFi
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
"M.2/M 2230"
"SlotDataBusWidth1X"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
"M.2/M 2230"
"SlotDataBusWidth1X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
register "srcclk_pin" = "2"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
register "srcclk_pin" = "2"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
device generic 0 on end
end
end

28
src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
View file

@ -179,16 +179,26 @@ chip soc/intel/tigerlake
device ref i2c4 on end
device ref uart2 on end
device ref pcie_rp9 on
register "HybridStorageMode" = "0"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "0x08"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieRpSlotImplemented[8]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
register "HybridStorageMode" = "0"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "0x08"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieRpSlotImplemented[8]" = "1"
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthOther"
"M.2/M 2280"
"SlotDataBusWidth4X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
register "srcclk_pin" = "3"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
register "srcclk_pin" = "3"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
device generic 0 on end
end
end

97
src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
View file

@ -38,21 +38,27 @@ chip soc/intel/alderlake
end
device ref pcie4_0 on # SSD x4
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)"
register "srcclk_pin" = "4"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)"
register "srcclk_pin" = "4"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
device generic 0 on end
end
end
@ -166,10 +172,10 @@ chip soc/intel/alderlake
end
device ref i2c0 on
chip drivers/i2c/hid
register "generic.hid" = ""STAR0001""
register "generic.desc" = ""Touchpad""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D11_IRQ)"
register "hid_desc_reg_offset" = "0x20"
register "generic.hid" = ""STAR0001""
register "generic.desc" = ""Touchpad""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D11_IRQ)"
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end
@ -181,43 +187,54 @@ chip soc/intel/alderlake
end
device ref pcie_rp5 on # WiFi
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
"M.2/M 2230"
"SlotDataBusWidth1X"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
"M.2/M 2230"
"SlotDataBusWidth1X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
register "srcclk_pin" = "2"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
register "srcclk_pin" = "2"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
device generic 0 on end
end
end
device ref pcie_rp9 on # SSD x4
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_detect_timeout_ms = 50,
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_detect_timeout_ms = 50,
}"
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
smbios_slot_desc "SlotTypeM2Socket3"
"SlotLengthLong"
"M.2/M 2280"
"SlotDataBusWidth4X"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
register "srcclk_pin" = "1"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
register "srcclk_pin" = "1"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
device generic 0 on end
end
end

5
src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
View file

@ -161,6 +161,11 @@ chip soc/intel/alderlake
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
register "srcclk_pin" = "0"
register "is_storage" = "1"
register "add_acpi_dma_property" = "1"
register "skip_on_off_support" = "1"
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
register "use_rp_mutex" = "1"
device generic 0 on end
end
end