Guard function prototypes to allow the header to be used in ACPI
ASL code. The defines will be used in the next commit.
Change-Id: Id6c361155c914f168577833279b4b7cc317b2eec
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The function rtc_get_frequency_meter() already uses the wait_us() macro,
so the stopwatch variable "sw" is not needed.
Change-Id: I7e282b6ce881f4e8f9d5e1c92803fda363fe28d7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
MT8196 uses new RC mode with clk_buf driver, and needs srclken_rc to
send PMRC_EN. PMRC_EN will collect the requirements of all users,
such as MD, GPS, PCIE, NFC.
TEST=Build pass.
BUG=b:317009620
Signed-off-by: ot_song fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85842
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
MT8196 uses MT6685 clk_buf, and will use new RC mode with srclken_rc.
The clk_buf will provide several 26M clocks, and these clocks can be
independently turned on. RC mode will determine which clocks to be
turned on based on users' requests, which is collected into PMRC_EN
register by srclken_rc.
TEST=Build pass.
BUG=b:317009620
Signed-off-by: ot_song fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
With CB:85918 and CB:85930, we can clean up the TODO in mtk_dp_mask.
Follow DP Phy APIs to use `assert` for the param examination.
TEST=verified on Ciri and Navi
Change-Id: I94e6ad36d190d773876cbb43eb4ebe17164f3c92
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85931
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8196's eDP architecture is different from previous SoCs. DP Phy needs
to be configured during the initialization. Add read/write APIs for DP
Phy register configuration. Add a mock definition EDP_PHY_BASE for the
SoC that do not support DP Phy configuration.
BUG=b:382363408
TEST=emerge-geralt coreboot && emerge-rauru coreboot
TEST=check FW screen on Navi
Change-Id: I5c00d0aa7e35f03cc3c3aef6a58eadd3d334d8ed
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85914
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the functions that can be shared with MT8196 to dptx_hal_common.c.
BUG=b:382363408
TEST=emerge-geralt coreboot && emerge-cherry coreboot
TEST=verify FW screen on Navi
Change-Id: I9e151bc766c312eaf81b4220782775ef1c9d2297
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The layout of an extracted REEF shellball doesn't conform to the
usual ones used by other boards, so add a special-case handler for it.
TEST= run `bash croshfirmware.sh reef` and receive the correct firmware
image for the board.
Change-Id: Ib391f30a77b6aa75aa130ffb525e6e1d1239a588
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85873
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:315894234
TEST=Build pass.
The actual measurement of the average power over 20 seconds decreased
from 6.755W to 6.716W.
Change-Id: I71bda7055afc902525501ddf7074f9b2c5550d4a
Signed-off-by: Xavier Chang <xavier.chang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85663
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SoC like Glinda use different PSP MBOX offset.
Add config to allow SoC Kconfig to override PSP MBOX offset.
Change-Id: Iefcc7d3b75689b43399a7a7b612417c155619211
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85626
Reviewed-by: Ana Carolina Cabral
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add a devicetree option to disable the 48MHz clock output of the FCH
when an I2S audio codec uses a separate oscillator for its 48 MHz
master clock instead of the FCH clock output. This code was ported
from the Picasso code base.
Change-Id: I0c1bee121f528d28d591dace260507b345dfec26
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add STA panel STA_2082109QFH040022_50E serializable data to CBFS.
Datasheet: 2082109QFH040022-50E-XR109IB5T_Full viewing-300-51PIN-
V1.0.pdf
BUG=b:379810871
TEST=build and check the CBFS include the panel
BRANCH=corsola
Change-Id: I131e179b7c4420e2038ec4023f9b2f505fc6c088
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85889
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The link to the document 'A Tour Beyond BIOS - Implementing UEFI
Authenticated Variables in SMM with EDK II' is currently pointing to a
dead location at Intel's website. Fix it by changing it to point at
tianocore's github site and hope that this one will be more reliable
over time.
Change-Id: Ic6ba341cbd37edec142f8868ffe9ef677736b3dd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85916
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces an automatic linkage between the Microchip
EC (EC_GOOGLE_CHROMEEC_MEC) and ACPI memory
mapping (EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) options. This linkage is
enabled when the Microchip EC is selected.
Certain data registers in Microchip ECs cannot be accessed via I/O
space. Instead, an indirection mechanism is required for register
access. When using such an EC, coreboot must publish ACPI information
to access these data registers through ACPI data ports 66h/62h.
Analysis of the coreboot codebase has revealed that the
EC_GOOGLE_CHROMEEC_MEC and EC_GOOGLE_CHROMEEC_ACPI_MEMMAP options are
consistently used together. This commit streamlines this dependency by
linking the two options.
TEST=/sys/class/power_supply/BAT0/* reports consistent values on
fatcat board.
Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85886
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit enables ACPI memory mapping for fatcat boards featuring a
Microchip Embedded Controller (EC). This allows the operating system
to access and read various information from the EC.
The Microchip EC does not directly map these registers to I/O space,
necessitating the use of an indirection mechanism for register access.
TEST=/sys/class/power_supply/BAT0/* reports consistent values
Change-Id: I6fb1c2ab1418a9d7afaff07404e0a3dcba1d0eba
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Fix indentation to make it aesthetically more pleasing.
Change-Id: I51b052e4d9d358e92c8105cc23997d6d35bc4d8d
Signed-off-by: Andy <andy@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85895
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Place openSIL timepoints 1, 2 and 3 calls in the driver, which will
serve as the central point for invoking SoC-specific vendorcode
implementations. TP1 and TP2 will initialize silicon pre- and post-PCIe
enumeration, respectively. TP3 then performs late SoC IPs programming
and register locking closer to payload load prior to OS handoff. Add a
Kconfig option for selecting and including the openSIL driver source
code in the build.
Change-Id: If0559fc0ff0ec55e9ef131e5ed20dfb5baa651da
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85631
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an option, which defaults to disabled, to control whether the
GNA (Gaussian Neural Accelerator) is enabled. This is a device that
designed to handle AI tasks.
Change-Id: I99f015cf1b5e21e8b524c4aa9bd3e94f86908ca1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These are not needed as they are controlled via a power
resource that is specific to Intel Bluetooth.
Change-Id: I8502d03db3d43385ac19bc3c17a79232bde1aa94
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add common definitions and `mainboard_get_storage_type` API for
determining the storage type from mainboard.
TEST=emerge-rauru coreboot
Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85878
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is in preparation to store options in EFI variable store, rather
than CMOS. However, some still need to stay in CMOS, so that they can
be accessed via ACPI.
Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76582
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is done by edk2, so there isn't any need for coreboot to do it.
Change-Id: I947d5d2f7512cc910963054dfbe6b5dc0f00462a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Move the functions that can be shared with MT8196 to dptx_common.c.
BUG=b:382363408
TEST=emerge-geralt coreboot && emerge-cherry coreboot
Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85860
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add `_common` postfix to the header files located in
common/dp/include/soc/. The patch helps MT8196 managing its own DP
register difition and macros in its include/soc folder.
BUG=b:382363408
TEST=emerge-geralt coreboot && emerge-cherry coreboot
Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Increase the char buffer size to fit all characters that are printed
into it by the snprintf() call below.
Change-Id: Ib153e1d02a08b2551dad5b51c4c88bf0bb606af3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Store CR3 on stack and restore it when returning from protected
mode call, since the stage might have set up different page tables
than the default ones linked into all stages.
Tested: intel/archercity still boots to payload in x86_64.
Change-Id: If94a24925994ac9599be24f6454ea28d02ff0c67
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
FSP, that is build against EDK2 2018 or newer, is able to back up and
restore the bootloader IDT on entry/exit. Even though it sets up its
own IDT, FSP checks the bootloader IDT size and deadloops without
warning if it's too big.
On x86_64 coreboot the IDT is naturally bigger than on x86_32 and thus
x86_32 FSP might die on entry. Work around this issue by:
* Back up and restore the IDT in protected_mode_call_wrapper
* Load zero IDT in protected mode before jumping to function
TEST: Can boot on SPR FSP (x86_32) using x86_64 coreboot with
exceptions in romstage enabled.
Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85789
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
As suggested by the linter:
Prefer 'unsigned long' over 'unsigned long int' as the int is unnecessary
Link: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/artifact/lint.txt
Cc: "Jérémy Compostella" <jeremy.compostella@intel.com>
Change-Id: Ida1de23830b0b67ab7fac635b02a4e99c65746f8
Signed-off-by: Ariel Otilibili <otilibil@eurecom.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85782
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Correct the argument type of the mt6363_sdmadc_read API and the return
value type of the mt6363_read16 API.
TEST=Build pass
BUG=b:317009620
Change-Id: I0f768e23473fa924245d90ab1e4fa383ec437db3
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The MT6363 buck5 API's mask and shift settings are incorrect, preventing
the buck from being disabled. Resolve the issue by correcting these two
values.
BUG=b:365445188
TEST=build pass, check buck5 is power off after calling the
mt6363_enable_buck5 API.
Change-Id: I0af1e0582ae8fc1e219f3cce536aed9985108be5
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85838
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The initialization process of SPMI requires a certain amount of time
(0.5ms) to ensure all components are correctly configured and
synchronized. Otherwise, if the SPMI calibration fails, it will result
in the non-serial firmware failing to boot.
TEST=Build pass, non-serial firmware boot ok.
BUG=b:341054056
Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Previous redirect to the Wikipedia page for GPIO led to nowhere.
Change-Id: I22dc606623dbc32af463e4501f1f21c119453792
Signed-off-by: libreandre <openrc@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85868
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for reading core scaling factors via the
PCODE mailbox interface.
Starting with Lunar Lake, the scaling factor information is
centralized in the power control unit (PCU) firmware. In order to keep
all firmware in sync, it is recommended to read the scaling factors
from the PCU firmware instead of using hard-coded values.
The following changes were made:
- Updated the Kconfig file to select
SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS option
- Modified the acpi.h header file to export the cpu_perf_eff_type
enumeration for CPU performance/efficiency types.
- Added a new function to the pantherlake systemagent.c file,
soc_read_core_scaling_factors(), which reads the core scaling
factors from the PCODE mailbox interface. The pcode
READ_CORE_SCALING_FACTOR is presented in document 829201 Panther
Lake Processor Mailbox Command.
The performance impact on boot time is minimal. It took 12 us to read
the scaling factors on a fatcat device.
TEST=Successfully read performance and efficient scaling factors on a
fatcat board.
Change-Id: I7a8e1e66a02e4bf6b1a41277e83c6dec786fe169
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85554
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
