ec/google/chromeec/acpi: Add support for generic LPC memory range

This change adds support for the generic LPC memory range configuration
in the EC ACPI code.

If CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled, the
EC will use the generic LPC memory range for EMEM related communication
between EC and AP Firmware. This is useful for platforms that do not
have a dedicated IO range like accessed EMEM through port 62/66 or
through LPC at 900h.

The generic LPC memory range is defined by the _SB.PCI0.LPCB.GLGM()
method. This method returns the base address and size of the memory
range.

Update the comment section to reflect the alternative source for EMEM
data when CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is enabled.

BUG=b:354066052
TEST=Build and boot on a device with
CONFIG_EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE enabled.

Change-Id: I8038e2827ec7e301bad3a5a58df007f3a448bad7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2024-12-30 14:06:03 +00:00
commit 70b33cb38d
2 changed files with 5 additions and 1 deletions

View file

@ -108,6 +108,9 @@ Device (EC0)
OperationRegion (EMEM, EmbeddedControl,
EC_ACPI_MEM_MAPPED_BEGIN, EC_ACPI_MEM_MAPPED_SIZE)
Field (EMEM, ByteAcc, Lock, Preserve)
#elif CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE)
OperationRegion (EMEM, SystemMemory, \_SB.PCI0.LPCB.GLGM() + 0x100, EC_MEMMAP_SIZE)
Field (EMEM, ByteAcc, NoLock, Preserve)
#else
OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE)
Field (EMEM, ByteAcc, NoLock, Preserve)

View file

@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* EMEM data may be accessed through port 62/66 or through LPC at 900h.
* EMEM data may be accessed through port 62/66 or through LPC at 900h
* or through LPC GMR (Generic Memory Range) MMIO range.
*/
TIN0, 8, // Temperature 0