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mb/starlabs/*: Set ASPM and L1SS in devicetree

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Explicitly set ASPM and L1 Substates to maximum, to avoid instances
where the default "AUTO" in FSP will fail to detect the highest
level.

Tested on all devices, with Ubuntu 24.04 by verifying general
functionality of the connected device.

Change-Id: I9f156124925bebd8588d863661bb2702c552f657
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84727
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2024-10-11 11:49:03 +01:00
commit 33fdda93c0
5 changed files with 20 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
View file

@ -141,6 +141,8 @@ chip soc/intel/alderlake
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen4x1"
@ -153,6 +155,8 @@ chip soc/intel/alderlake
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X4"
"SlotLengthShort"
@ -164,6 +168,8 @@ chip soc/intel/alderlake
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X4"
"SlotLengthLong"

4
src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
View file

@ -143,6 +143,8 @@ chip soc/intel/alderlake
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"
@ -160,6 +162,8 @@ chip soc/intel/alderlake
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_detect_timeout_ms = 50,
}"

4
src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
View file

@ -35,6 +35,8 @@ chip soc/intel/alderlake
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypeM2Socket3"
@ -173,6 +175,8 @@ chip soc/intel/alderlake
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"

4
src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
View file

@ -41,6 +41,8 @@ chip soc/intel/alderlake
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypeM2Socket3"
@ -186,6 +188,8 @@ chip soc/intel/alderlake
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypePciExpressGen3X1"
"SlotLengthShort"

2
src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
View file

@ -149,6 +149,8 @@ chip soc/intel/alderlake
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L0S_L1,
.PcieRpL1Substates = L1_SS_L1_2,
}"
smbios_slot_desc "SlotTypeM2Socket3"