mb/starlabs/*: Configure GPIO UPDs for eSPI

FSP defaults to using pins that are used for LPC; given that
coreboot and these boards only supports eSPI, set these pins
accordingly.

If this is not done, FSP will assert and not boot.

Change-Id: Ide4d92211fa7ab496c38ce1c4e895337c269d247
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk

@@ -7,3 +7,4 @@ romstage-y += romstage.c
 ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
+ramstage-y += ramstage.c

src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
+{
+	/*
+	 * FSP defaults to pins that are used for LPC; given that
+	 * coreboot only supports eSPI, set these pins accordingly.
+	 */
+	supd->CnviRfResetPinMux			= 0x194ce404;	// GPP_F4
+	supd->CnviClkreqPinMux			= 0x294ce605;	// GPP_F5
+	supd->SataPortDevSlpPinMux[1]		= 0x5967400d;	// GPP_H13
+}

src/mainboard/starlabs/starbook/variants/adl/ramstage.c

@@ -3,9 +3,16 @@
 #include <option.h>
 #include <soc/ramstage.h>
 
-
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
+	/*
+	 * FSP defaults to pins that are used for LPC; given that
+	 * coreboot only supports eSPI, set these pins accordingly.
+	 */
+	supd->PchSerialIoI2cSdaPinMux[0]	= 0x1947c404;	// GPP_H4
+	supd->PchSerialIoI2cSclPinMux[0]	= 0x1947a405;	// GPP_H5
+	supd->SataPortDevSlpPinMux[1]		= 0x5967400d;	// GPP_H13
+
 	/*
 	 * Enable Hot Plug on RP5 to slow down coreboot so that
 	 * third-party drives are detected.

src/mainboard/starlabs/starbook/variants/rpl/ramstage.c

@@ -3,9 +3,15 @@
 #include <option.h>
 #include <soc/ramstage.h>
 
-
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
+	/*
+	 * FSP defaults to pins that are used for LPC; given that
+	 * coreboot only supports eSPI, set these pins accordingly.
+	 */
+	supd->PchSerialIoI2cSdaPinMux[0]	= 0x1947c404;	// GPP_H4
+	supd->PchSerialIoI2cSclPinMux[0]	= 0x1947a405;	// GPP_H5
+
 	if (get_uint_option("thunderbolt", 1) == 0)
 		supd->UsbTcPortEn = 0;
 }

src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c

@@ -3,9 +3,15 @@
 #include <option.h>
 #include <soc/ramstage.h>
 
-
 void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
 {
+	/*
+	 * FSP defaults to pins that are used for LPC; given that
+	 * coreboot only supports eSPI, set these pins accordingly.
+	 */
+	supd->PchSerialIoI2cSdaPinMux[0]	= 0x1947c404;	// GPP_H4
+	supd->PchSerialIoI2cSclPinMux[0]	= 0x1947a405;	// GPP_H5
+
 	if (get_uint_option("thunderbolt", 1) == 0)
 		supd->UsbTcPortEn = 0;
 }

src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk

@@ -7,3 +7,4 @@ romstage-y += romstage.c
 ramstage-y += devtree.c
 ramstage-y += gpio.c
 ramstage-y += hda_verb.c
+ramstage-y += ramstage.c

src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
+{
+	/*
+	 * FSP defaults to pins that are used for LPC; given that
+	 * coreboot only supports eSPI, set these pins accordingly.
+	 */
+	supd->CnviRfResetPinMux			= 0x194ce404;	// GPP_F4
+	supd->CnviClkreqPinMux			= 0x294ce605;	// GPP_F5
+	supd->PchSerialIoI2cSdaPinMux[0]	= 0x1947c404;	// GPP_H4
+	supd->PchSerialIoI2cSclPinMux[0]	= 0x1947a405;	// GPP_H5
+}