Enable the GNA PCI device, and include the ACPI stub so the OS driver
can attach.
TEST=build/boot Win10 on google/dedede (magpie)
Change-Id: I928bfe710e69bb43f177e3ce0c0077638233d44d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77579
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are used to control the rails, so enable them.
Change-Id: I3607dad4e57b99048aa7669c826fed046554333a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Determine CPU frequency & voltage for use in smbios type 4 table.
Reference:
AMD PPR 57254 v1.59 Section 2.1.15 CPUID Instruction
TEST=Build for glinda SoC & verify output to reflect CPU frequency
& voltage.
Sample Output:
dmidecode -t
...
Voltage: 1.2 V
...
Current Speed: 2600 MHz
...
Change-Id: Ibd7c7f1e299a0a8d294e7e30ae3130faae16ae22
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86757
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the generic x86 SPI flash mmap driver is being used when not
using DMA and when not on GENOA. It only works for ROM_SIZE of 16 MiB
or less and prevents boot when the ROM is bigger than that.
Use the genoa_poc SPI MMAP driver on all platforms by default as it
allows to use a ROM_SIZE greater than 16MiB. The newly introduced
Kconfig SOC_AMD_COMMON_BLOCK_SPI_MMAP is used for all platforms when
the SPI DMA driver is not in use.
This doesn't allow to access the whole SPI flash using the ROM2 MMIO
window, but it no longer prevents boot when the mainboard specifies
the correct SPI flash size in Kconfig.
TEST: Booted an AMD/birman+ with 64MiB ROM specified in Kconfig.
TEST: Booted on AMD/onyx with 32MiB ROM specified in Kconfig.
Change-Id: I39e33c71d27179212ddb1f5bcca4c5d4a39d47e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86618
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add functions to return the position and size of the ROM2 and ROM3
MMIO windows that mmap the SPI flash. Starting from AMD Family 17h
Model 30h (Zen 2) the ROM3 BAR is available.
ROM3 is not supported on picasso or stoneyridge.
Document ID: 56780
TEST: Verified that both functions return sane values.
Change-Id: I10d4f0fe8a38e0ba2784a9839270d5dd3398d47a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the LPC PCI device to make sure common code builds.
Document ID: 55898
Change-Id: I52b129b47f98d88cad1d656dab4d4562c7ce3394
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86706
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds initial dq mapping and spd data for LP5 memory
parts for GCS board. This also configures memory based on the board id.
Memory - LPDDR5x
Vendor/Model - H58G66BK8BX067
BUG=b:398880064
TEST=Boot to OS on GCS board.
Change-Id: I268ddf2d4b6361d9dabb217c4246cb6cc0e2144c
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Commit 3ff85e5dcd ("soc/intel/alderlake:
Make Energy Efficient Turbo configurable") made the EnergyEfficientTurbo
User Product Data (UPD) adjustable, but it did not update the comment.
Change-Id: I34b8829efcfa3210950051e9b6d4d5a3c289ec93
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces the missing Fast Voltage Mode settings for the
Voltage Regulator (VR) applicable to the Intel Panther Lake (PTL)-U 15W
System on Chip (SoC) on the Google Fatcat mainboard. The configurations
have been populated in accordance with the specifications outlined in
Intel's Panther Lake Power Map document (reference number 813278). These
settings leverage the Fast Voltage Mode capabilities of the CPU cores
(IA), Graphics (GT), and System Agent (SA).
The voltage regulator settings are for PTL-U; therefore, when the
coreboot image is used on a Panther Lake H SKU, some lower performance
could be observed due to the I_TRIP value being lower than what the
device could actually use.
BUG=b:357011633
TEST=As no Panther Lake-U (PTL-U) SKUs were available, smoke tests have
been performed on Panther Lake-H (PTL-H). We verified that the
Firmware Support Package (FSP) successfully submitted requests to
the pcode firmware and that once the operating system was running,
S0iX entry and exit were operational.
Change-Id: If98edb88d7488c0b863a8f1a9654d0273de567c6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Micron SPD file was removed and Nanya-NT6AP512T32BV-J1I.spd was added
as it will be used for the final product.
Change-Id: Icbfb3a51fcb7c09bad9b70861fa58f5c957ce1ae
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86423
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Add joxer new supported memory part in mem_parts_used.txt.
DRAM Part Name ID to assign
H58G56CK8BX146 5 (0101)
BUG=b:236576115
TEST=USE="project_joxer emerge-nissa coreboot"
Change-Id: I4045e895694b940748b5f221ebcabaa4be064b95
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The Intel Hayden Bridge Re-timer drives I2C SDA low unexpectedly
which breaks the I2C communication between EC and TCPC and causes
multiple USB-C issues. This patch sets HBR FORCE_PWR pin high by
default to prevent the HBR from entering low power state to work
around the I2C issue.
BUG=b:386019934,b:380947618
TEST=Verify basic USB-C functions on Deku
Change-Id: I6eae8ad4ae1b22446b903fad276a3fbcd57ca865
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add the same wakeup method that Alder Lake uses to Meteor Lake.
Test=boot `starlabs/starbook/mtl` and check USB devices can wake.
Change-Id: I67da6af619db947ab4830fa2d9904f3e70fbfd21
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86628
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
MT8188, MT8192 and MT8195 use mt6359p RTC and share the same RTC
definitions. Move the definitions to rtc_mt6359p.h and remove duplicate
definitions.
BUG=b:391067089
TEST=build coreboot for asurada, cherry and geralt
Change-Id: I6e60148e1847171c6ab6b6dbee2fd706f3c3a47f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The MediaTek RTC driver does not check the return value of rtc_read()
and rtc_write(). Additionally, the RTC driver of recent platforms uses
void for rtc_read() and rtc_write(). Therefore, change the return type
of all rtc_{read, write} APIs to void and add assert for debugging.
BUG=b:388796896
TEST=build coreboot for elm, kukui and corsola
Change-Id: Ie5168db0abd479e63279ac4c8d6f2c668d6234f0
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MT8173, MT8183 and MT8186 read and write RTC register via pwrap
interface. Since the implementations are the same, move those APIs to a
common file.
BUG=b:388796896
TEST=build coreboot for elm, kukui and corsola
Change-Id: I6c177e8c1b5dee72c18d765f19a48eb38db121f1
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Enable Port Reset on USB lanes corresponding to Type-C ports on the
mainboard.
Change-Id: Id9adc8827f3393e419118efda91c06c43ebb2ccb
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86843
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel I210 Ethernet Transceiver is not used on the platform.
As there are dependencies in the mainboard code that references
functions defined by I210 code a new header (tsn_gbe.h) was added as it
contains the dependent function definitions. The corresponding TSN_GBE
driver will be used anyway on the platform. Thereby dependencies that
lead to a failed build should be resolved with this commit.
Change-Id: I413cb334ee06e3fc7183dc2621b6091f0d0b602b
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
vGPIO configs are configured to enable SSP2 for BT audio offload.
BUG=b:404741604
Test=Verified BT offload with HDA configuration
Change-Id: Ibce828e32f4640cb234591392bb6ebf0662105fc
Signed-off-by: Monika A <monika.a@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Introduce support for an IPC mailbox interface that lets the OS
exchange commands and responses with the Power Management Controller
(PMC) when needed.
Change-Id: Id6748b410b96dcf2a6e681c39dad2173be9bde3c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86916
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the GPIO that enables eSPI to PLTRST to ensure that eSPI works
in S3.
Change-Id: I7da5cf493a676ea106ab94fcb377bc8a29b72990
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This pins aren't connected to anything so adjust them accordingly.
Change-Id: I906e3b555e7ae802f6c14285ad8a5b98f43b2f36
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Enable the High Definition Audio Digital Signal Processor (HDA DSP)
to improve audio processing capabilities.
Change-Id: I6fd44b40a635bc6bb9404978493761823088b0fa
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86917
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Display-Alt Mode doesn't require HPD to be set here, so remove it.
Change-Id: I6e03c481584ff2b0bbb06d1d21f31fd0db4ecb27
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86915
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Deselect this so that a local copy of PR3 can be used.
Change-Id: I7efe35457186bca43af3e5b7557cbd3be6cecbb7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86913
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Leave the rcomp config empty so that 0's are passed to FSP; this
allows FSP to figure out the correct settings to use.
Change-Id: Id7d44984c5ecfd0307d207d997248e88e1bd6eb4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The default for DQS interleaving is 0, so don't set it to 0.
Change-Id: I5f828aa3a28947c2f88eaf36cc7bc8ad68812cb2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
`ddr5_spd_info` is a better name for DDR5 memory parameters.
Change-Id: If54718592950164569fccee6e8b7d53803310de0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This enables the utility crossystem to access WP GPIO.
BUG=b:399511940
TEST= wpsw_cur in crossystem reads the correct gpio
Change-Id: Ided919920dff74c49ce2f718f845ae5a1117a89b
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86923
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
According the schematic to correct PCIe RP 11 for WIFI7.
BUG=b:388117663
TEST=build pass and insure WLAN function work properly
Change-Id: I84e9fc707c23099d7cd7ea2d8acde1043325f06b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86934
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Enable PCIE port 7 using clk 3 for RTL8111H Ethernet.
BUG=b:388117663
TEST=build pass and insure LAN function work properly
Change-Id: I60c30f207aa92ba9f52da0b95b647307a73e9d13
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86930
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This reverts commit c476c4d5b9.
Reason for revert: Previously in CB:85799, we added a 0.5ms delay as a
workaround to solve the boot hang issue of non-serial firmware. Now that
the root cause has been identified and fixed in CB:86859, we can revert
the workaround.
Original change's description:
CB:85799, commit c476c4d5b9 ("soc/mediatek/mt8196: Delay 0.5ms after
enabling PMIF SPMI SW interface")
BRANCH=rauru
BUG=b:341054056
TEST=Build pass.
Change-Id: I0abdcae95924c4d3197496c14d20502b08938d76
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Currently, we don't explicitly disable the PMIF and SPMI resets after
the reset is completed, causing them to remain asserted for
approximately 0.5ms. That would cause the DUT to hang during PMIF
initialization (pmif_spmi_init) when using non-serial firmware.
To fix this issue, explicitly disable the PMIF and SPMI resets
immediately after the reset.
BRANCH=rauru
BUG=b:341054056
TEST=Build pass, non-serial firmware boot ok.
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: Ic903ddd893470cd46dbfed9c3faa9c2a9e50c904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86859
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Meliks uses GPP_E7 to determine the channel count of the RAM chip in
romstage, move its configuration to early_gpio_table from
override_gpio_table to be ready to use at that moment.
And early stage meliks boards didn't implement the GPP_E7 strap but
leaved it as NC. All of them used two channel ram chip, so add DN_20K
for them not to disable any memory channel. Otherwise, they might not
be able to boot since memory training will be failed due to the
incorrect memory channel information.
BUG=None
BRANCH=nissa
TEST=FW_NAME=meliks emerge-nissa coreboot
Change-Id: Icf71c3a1f24d3dcbff6ba5e646e9f805144add71
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86908
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch corrects spacing around assignment operators in the
`fill_blt_buffer` to comply with coding style guidelines, specifically
within the BMP color translation logic for 1/4/8/24/32-bit images.
Change-Id: Ia243d11568ec4c3d1108ff60289743919394aa32
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86860
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Windows doesn't have / will likely never have a signed driver for the
FPR, so set the device status as hidden so it will not appear as an
unknown device in Windows Device Manager. Linux does not check/care
about the ACPI device status.
TEST=build/boot Win11 on google/guybrush (nipperkin), verify FPR does
not show up as unknown device under Device Manager.
Change-Id: I3eac631aebb26ec1c375b436e088be522d659338
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86847
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces new board ID definitions for PTL-P and GCS in the
PTLRVP mainboard code. The changes involve updating the `romstage.c` and
`memory.c` files to handle these new board IDs, ensuring that memory
configuration is correctly initialized based on the detected board
type.
Change-Id: Ia354db27a0124dcde2825e7a05a59ef5d539c4ef
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The PSP_SOFTFUSE_BITs were probably copy&pasted during initial
SoC bringup and need to be adjusted:
* Drop PSP_SOFTFUSE_BIT BIT28 as it causes PSP to hang.
* Drop PSP_SOFTFUSE_BIT BIT34 as it's not required.
This also moves coreboot closer to the UEFI reference firmware.
Document #55758 Rev. 2.04
TEST: Booted on amd/birman_plus with default PSP_SOFTFUSE_BITS.
Change-Id: Ic7b2b0ac01fe0ac0ed2535254f242a8068f9b02a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86840
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Don't set this, so FSP will use the default auto setting, which
behaves better with various memory sizes.
Change-Id: I4d0bfd19af08ec127065f7ad5aaa51cb7e0ca2ac
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86905
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the High Definition Audio Digital Signal Processor (HDA DSP)
to improve audio processing capabilities.
Change-Id: Ifcd107f0c889fc5210bdb8578d1df27b9e4414ff
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86903
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce support for an IPC mailbox interface that lets the OS
exchange commands and responses with the Power Management Controller
(PMC) when needed.
Change-Id: I31ba44dc6fb848dda94321e1c17e64ddf6abe637
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86902
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure all the controlling GPIOs to IOSTANDBY_IGNORE to
ensure they work in S3.
Change-Id: I1b34793a6437d2e489fca90be1f5d3e13ec7d559
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Don't configure the eSPI GPIOs as they are configured automatically on
reset.
Change-Id: Icdd6e916571bad33404fa91a1e288e0a18d7778b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set the GPIO that enables eSPI to PLTRST to ensure that eSPI works
in S3.
Change-Id: Ibee64ccd9f21f33b764aacc4f97404ba56e5102e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set the PMC alert and SML Clock/Data pins to IOSTANDBY_IGNORE to ensure
that they're still operational in S3.
Change-Id: I1dd7a9410211c50cc171645f6db82b15c52ff7ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
