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mb/google/fatcat: Add PTL-U Fast VMode Voltage Regulator settings

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This commit introduces the missing Fast Voltage Mode settings for the
Voltage Regulator (VR) applicable to the Intel Panther Lake (PTL)-U 15W
System on Chip (SoC) on the Google Fatcat mainboard. The configurations
have been populated in accordance with the specifications outlined in
Intel's Panther Lake Power Map document (reference number 813278). These
settings leverage the Fast Voltage Mode capabilities of the CPU cores
(IA), Graphics (GT), and System Agent (SA).

The voltage regulator settings are for PTL-U; therefore, when the
coreboot image is used on a Panther Lake H SKU, some lower performance
could be observed due to the I_TRIP value being lower than what the
device could actually use.

BUG=b:357011633

TEST=As no Panther Lake-U (PTL-U) SKUs were available, smoke tests have
     been performed on Panther Lake-H (PTL-H). We verified that the
     Firmware Support Package (FSP) successfully submitted requests to
     the pcode firmware and that once the operating system was running,
     S0iX entry and exit were operational.

Change-Id: If98edb88d7488c0b863a8f1a9654d0273de567c6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Jeremy Compostella 2025-02-27 09:20:34 -08:00 • committed by Matt DeVillier
commit d19dd192db
1 changed files with 17 additions and 0 deletions
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17
src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
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@ -62,6 +62,23 @@ chip soc/intel/pantherlake
# Enable Energy Reporting
register "pch_pm_energy_report_enable" = "true"
# As per document 813278, the Intel PTL-U 15W SoC supports
# Fast V-Mode (FVM) on cores (IA), Graphics (GT), and System
# Agent (SA). The ICC Limit is represented in 1/4 A
# increments, i.e., a value of 400 = 100A.
# IA VR configuration
register "enable_fast_vmode[VR_DOMAIN_IA]" = "true"
register "cep_enable[VR_DOMAIN_IA]" = "true"
register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "252" # 63A
# GT VR configuration
register "enable_fast_vmode[VR_DOMAIN_GT]" = "true"
register "cep_enable[VR_DOMAIN_GT]" = "true"
register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "152" # 38A
# SA VR configuration
register "enable_fast_vmode[VR_DOMAIN_SA]" = "true"
register "cep_enable[VR_DOMAIN_SA]" = "true"
register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "152" # 38A
# Enable CNVi BT
register "cnvi_bt_core" = "true"