This patch adds three more parts that are used in Lenovo Thinkpads:
SKHynix H5AN4G6NAFR-UHC
SKHynix H5ANAG6NAMR-UHC
Micron MT40A512M16LY-075:H
The settings (MT/s, timing, organization, etc.) have been obtained from
schematics and datasheets.
Change-Id: Ie0958a4a845f072daee3379731f558584dca5da6
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This fixes an error I made in my previous commit 8a83b86254 (spd/ddr4:
add parts), CB:90032. The package bus width for all the dual die parts
is indeed 16 rather than 8. This has been validated when porting
coreboot to the Lenovo Thinkpad X280 that uses soldered-on DDP RAM
(Samsung K4AAG165WB-MCRC).
Change-Id: I8baa7c979074584e65772315e66e787cef3202e4
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Peppy has two touchpad options, and having the ACPI device for both
enabled under Windows causes issues, as they use the same resources.
Since Peppy can't use the runtime detection feature supported by
newer platforms, add a CFR menu option to select between the two.
Default to both touchpad devices being enabled, so that there
is no change in behavior until the user changes the option.
TEST=build/boot Win11/Linux on google/peppy, verify touchpad
functional under both OSes when correct touchpad type selected,
and functional under Linux when Auto-detect is selected.
Change-Id: I0e63a252cd5bbc04244c9999b7586480891013a5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Haswell/Lynxpoint/ChromeEC.
TEST=build/boot google/wolf, verify CFR option functionality.
Change-Id: Ife64d46a9866c67fbb941cc83428f7728c6f7f95
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tidy up before adding a new entry.
Change-Id: Ib37c9b4b73819b1309a7c2405830f1524e3d3f74
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Some LULU boards are equipped with a touchscreen, others are not. Since
Broadwell doesn't support the use of the i2c generic driver and runtime
detection, add a CFR menu option to allow selective disabling of the
touchscreen ACPI device by users whose boards do not have one.
This prevents a malfunctioning touchscreen device from appearing in
Device Manager under Windows.
TEST=build/boot lulu, boot Win11, verify no malfunctoning touchscreen
device shown in Device Manager when disabled in CFR option menu.
Change-Id: I423ef1cf085bc488b4740092b992a245e3fd7e7e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90166
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR option menu support when using edk2 payload and SMMSTORE.
Include relevant items from Broadwell Soc and ChromeEC.
TEST=build/boot google/lulu, verify CFR option functionality.
Change-Id: I9a5d61464cbf88b621c38a3779a7409977f20bed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90165
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tidy up before adding a new entry.
Change-Id: I33b0b4cf99534eb9dbc28d43286656488d1f498c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90164
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The camera ACPI code was likely copy/pasted from another board, and
while the ACPI itself is correct, the comment is not. Fix the comment
to match the code / actual board config.
TEST=n/a; this change is non-functional.
Change-Id: I10eb20d9f51e1bc0cd4589c11ac39d23ed836bf4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Set FPR (Fingerprint Reader) device status to hidden to prevent
Windows from enumerating it, as Windows does not support the FPR
on this platform. Linux ignores ACPI device status and continues
to work correctly via direct SPI access.
TEST=build/boot Win11, Linux on Nocturne.
Change-Id: I8806cbef3acbab45ddd03e9fa80f79625c84bcb4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90156
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove EC feature definitions that are not supported by the
puff EC firmware:
- LID switch (CONFIG_LID_SWITCH is undefined)
- PS/2 keyboard (CONFIG_CMD_KEYBOARD is undefined)
- Keyboard backlight (not configured)
Also remove corresponding host event masks from SCI, SMI, and
wake event definitions.
All of these were remnants from puff originally being part of the
hatch mainboard, from which it was split off.
TEST=build/boot google/puff/var/wyvern
Change-Id: Idd86d4f342d29a25bd640d480cd5834e6250bcf0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90155
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The GPIO config in the tree does not allow for S3 resume to work, as
the eSPI Virtual Wires stop reponding when the system enters S3.
Through setting the GpioOverride UPD to 0, the configuration in this
patch was discovered. This configuration keeps the virtual wires
working, and in turn, S3 resume works.
Change-Id: I5f73f74970d70f7736aa019a8e37e898921ae740
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add IGD PCI ID of Xeon W-11865MRE to graphics driver so coreboot can use
GOP-provided framebuffer.
TEST=Debug log shows framebuffer info at PCI: 00:00:02.0 init
Change-Id: Ifd76707d2ad61e11028cd0e19cf06857c597d514
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add the I3C controllers to the ACPI tables. Most of the ACPI code needed
for that is added to the DSDT, since everything, but the enable status
of the I3C MMIO devices is known at build-time. To handle the I3C
controller enable status, each ACPI device contains the STAT name with
the value of 0 in the DSDT and when the device is enabled this STAT name
will be overridden in the SSDT.
TEST=OS loads the I3C kernel modules on amd/birman_plus.
Change-Id: I309d54c81056486573c32d4da54de61b36b5c378
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
The following error is observed in Linux:
[ 30.255680] ACPI Error: Aborting method \_SB.FUR4.AOAC._OFF due to previous error (AE_AML_LOOP_TIMEOUT)
It caused a boot delay issue in the virtualization case above due to
some mmio regions not being passed through and the acpi interpreter
waiting.
reserve MMIO regions which are used by ACPI code in order to fix this
issue.
source: "Address Space Mapping" Table in relevant PPRs.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ia12a3dea0e24ae24fa1f7db7c7f2bd9f7dd6a591
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add missing HAVE_ACPI_RESUME Kconfig selection to enable S3
(suspend-to-RAM) sleep state support on Brya-based boards.
Without this option, the ACPI sleepstates.asl initializes SSFG to
0x09 (supporting only S0 and S4) instead of 0x0D (supporting S0, S3,
and S4). This prevents the _S3 ACPI object from being created in the
DSDT, causing the operating system to not recognize S3 as an
available sleep state.
With this change:
- SSFG is initialized to 0x0D
- _S3 ACPI object is created in DSDT
- Linux recognizes S3 as supported (dmesg shows "ACPI: PM: (supports
S0 S3 S4 S5)")
- Both s2idle and deep sleep options become available
Tested on Yaviks (Nissa/PCH-N variant).
Change-Id: I07cfe9327b73d28ba7f7abc7755f3b870be5be00
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90252
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix several HDA pin configuration issues:
- NID 0x06 (Internal Speaker): Disable jack presence detection.
- NID 0x08 (Unused): Standardize to AZALIA_PIN_CFG_NC(0) which
generates the canonical NC value 0x411111f0 instead of the
non-standard 0x77a70037.
- NID 0x09 (Internal Digital Mic): Disable jack presence detection.
This resolves an issue under Linux where the speakers would keep
outputting audio when the headphones were plugged in.
Change-Id: If9f5781200e2d2dc6c90713caf999868f7b993a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Convert raw hexadecimal pin configuration values to use the
AZALIA_PIN_DESC macro for improved readability and maintainability.
All pin configurations have been verified to generate identical
binary output to the original raw verbs:
- NID 0x05: Headphone Jack (0x022110f0)
- NID 0x06: Internal Speaker (0x901700f0)
- NID 0x07: Microphone Jack (0x02a110f0)
- NID 0x08: Unused/NC (0x77a70037)
- NID 0x09: Unused/NC (0xb7a6003e)
- NID 0x0a: SPDIF Out/NC (0x434510f0)
No functional changes.
Change-Id: Ib2f531575dd0e3cccf41b74e861394f21ce237af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
When BOX3.XBCM fails we currently fall back to LEGA.XBCM, which writes
directly to the IGD PWM registers. During S3 resume those registers are
still reset by the graphics driver, so AML stores a zero duty cycle and
the panel stays dark. This leads to having some other event needed to
wake the panel (i.e. key press).
Only invoke the legacy path after BCLM is initialized, matching when the
driver has reprogrammed the PWM registers and preventing firmware from
touching them while the driver is still restoring them.
Test=Enter and exit S3 on starbook_mtl, verify that the display turns on and stays on, instead of on -> off -> on.
Change-Id: I664d296372feef9de5c4f57428422328c4e33110
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89985
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The devtree.c was trying to disable the incorrect USB port, 3.
Correct this to 7.
Change-Id: Ibae3d104d2887706dbe2e1c13e817eeee644b5ad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The FSP structs are usually typedefs and are also used like that across
the tree.
In order to make this file usable for code inside our tree
(specifically AMD) change it to typedefs.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ie799e0116997ba559b990a9b3a2038fea852d8ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
GPP_F08 -> EN_TCHSCR_PWR
GPP_F16 -> TOUCHPANEL_RESET#
Adjust touchpanel's power on timings:
1. EN_TCHSCR_PWR go high before L_VDDEN_PCH during power on
2. TOUCHPANEL_RESET# high after EN_TCHSCR_PWR high when power on
BUG=b:462913972
TEST=emerge-fatcat coreboot
the EE measured the power-on timing of the touchscreen, and it met the requirements.
Change-Id: I4e50223477003ff93d4751527196894cc0a3e781
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90243
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add MT62F1G32D2DS-031RF WT:C in the memory_parts.json and re-generate
the SPD.
BUG=b:459934066
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Ib65f24347ddae2808720f8e3c73652a82de94311
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90019
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard has an LED that shows when coreboot has finished. The LED
is switched on via GPIO GPP_F4.
TEST=LED turns on when booting to Payload.
Change-Id: Ia292b10573d67df3f288b97fa2e92ae85ba7f27b
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90201
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the feature to send POST codes to the NC FPGA via PCI. This
allows the POST codes to be visible on the embedded 7-segment display
during coreboot runtime.
Further sort switches in alphabetical order.
TEST=Build and boot mc_ehl6. Verify that the POST Codes are
correctly displayed on the embedded 7-segment display.
Change-Id: Ie7e4961c0345312126eb2000c2934e33fce3b584
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Activate SATA interface port 1 for mass storage connection on mc_ehl6
mainboard.
Function of SATA_LED_N and M.2_SSD_SATA_DEVSLP_1 are not used.
TEST=Check mass storage in running OS.
Change-Id: I34ca0d71a04c4338e35bcf9ede4ccef41efab01e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This patch changes the LED settings for used Marvell PHY 88E1512 driver
of PSE GbE 0 and PCH GbE on mc_ehl6 mainboard.
The interrupt functionality on Marvell PHY 88E1512 is not used in the
OS for this board. In this Phy the interrupt is multiplexed with LED[2]
Pin.
On mc_ehl6 mainboard LED Pins [0/1/2] are used.
- LED Pins [0/1] for two color LINK LED at the interface
- LED[2] for ACT LED
Driver parameters are set accordingly.
TEST=Boot into OS and check LINK and ACT LED at the related plugs at
100 and 1000 Mbit mode.
Change-Id: If7fd314034b35de67fc0b10e6be9b7578807cbff
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Remove the unused PSE TSN GbE device #1. This device is not
required for the current board functionality and removing it
simplifies the configuration.
TEST=Check if all other GbE ports of mainboard still work.
Change-Id: I8b23064ecff5fe67da3d847bb769784f8b3a15cc
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90086
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard uses native function two of GPIO B23 (PCHHOT_N) to
realise overtemperature behaviour of the mainboard.
TEST=Check the signal during HW commissioning and influence of heat to
the CPU.
Change-Id: I4caa88316d5027f7b9d74293a74377915f274766
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90085
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable PCIe PTM (Precision Time Measurement) for all enabled PCIe root
ports. The time synchronization is mainly necessary for stable timing to
PLC.
TEST
Boot in a standard linux OS and check if PTM ist enabled for active RPs
via lspci -vv -s 00:1c.0..6 | grep PTM
Change-Id: I965ab349c07158d0c69b9112571aa98575eada77
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90084
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Adapt I2C controller configuration for mc_ehl6 board. This involves
changes to the coreboot I2C setup. To prevent higher I2C speeds from
being used by the OS, dummy devices are installed on the I2C bus.
TEST=Check if drivers for the I2C devices started correctly during
coreboot execution and verify that all I2C devices are detected in the
OS.
Change-Id: I6de578f969456a15807a1380209ea18e01f522bd
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This patch adds the Display Stream Compression (DSC) related structures
to the panel header. These structures define the rate control parameters
and configuration options required by the DSC engine for frame
compression, such as quantization parameter ranges, bits per group
offset, compression enable flag, dual DSC support, and line buffer
depth.
BUG=b:424782827
TEST=Build pass, boot ok, display ok
Change-Id: Icec24f55b962cd2794a79a68fc8fecec43300103
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90129
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is one too many `endif` in this file. The only reason why jenkins
never complained is because this is apparently never included (and
therefore never compiled) by any code/mainboard in our tree.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id68d91d5c5365000fc97815d184d48f4b71bcb35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Adds skeleton code so that the HEST ACPI table is included as part of
the ACPI tables propagated to the OS.
The ACPI table can be included by mainboards by selecting
SOC_AMD_COMMON_BLOCK_ACPI_HEST.
TEST=Select the option, build the mainboard and see the output in Linux:
[ 0.282277] HEST: Table parsing has been initialized.
Change-Id: I69886a19764d6974cbe129a8a6bf717f7808fb08
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88113
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
This moves all the definitions and declarations that are part of the
ACPI Platform Error Interface (APEI) into the corresponding header file.
Change-Id: Ied3915e4f598cd393f396de26b07ade7ce3a7ab1
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Increase the bootblock size to 70K to accommodate its growth, e.g.,
CB:90147 and CB:89157.
This commit also conditionally includes the DRAM_INIT_CODE section when
ENV_ROMSTAGE is enabled, and the BOOTBLOCK section otherwise. This
allows increased BOOTBLOCK overlapping with DRAM_INIT_CODE as these two
sections won't be utilized in the same boot stage.
TEST=emerge-geralt coreboot
Change-Id: Ib7b930fbb1815d2f24b9618d94a38d02c66eab97
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90251
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Modify usb3 port 0 and 1 settings by vendor's advices.
BUG=b:446771934
TEST=Build and boot to OS, check usb3 functions work by lsusb -t.
Change-Id: I9ed47ead1b2ef0b007897513ceb99e9460875bdc
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This change mutes the amplifier by updating the HDA verb table boot beep
section, which is configured at boot time. The amplifier will be unmuted when
generating a dev beep to preserve that functionality.
After entering OS, the kernel will reset the drivers and re-enable the
speaker.
BUG=b:457933720
TEST=Play audio in the OS and reboot the device. Verify that no pop
noise is heard from the speakers.
TEST=Verify devbeep function
Change-Id: I19ef19533d8ed7522e638787c8179ae0fdbf1ebb
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90238
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The renoir variant has larger APOB data.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7b7da3b35f2795deb785f82326f3e6c640f6e9ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Renoir actually supports warm reset, so we don't need to toggle the
PwrGood for all resets.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I45d6b559874d67b886c65f7ad722f96eba415399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90211
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Unable to passthrough the UART0 in domU when UART1 enabled in dom0
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7ccf366dbac556f68096382644f3e72b13e2dbf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90210
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PSP_ADDR_MSR is programmed into the BSP by FSP, but not always
propagated to the other cores/APs. Add a hook to run a function
which will read the MSR value from the BSP, and program it into the
APs, guarded by a Kconfig.
It only writes the MSRs of the APs if they are not initialized yet.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I45771e596ac4354dd233a47fcae33012d9c0a6c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
