mb/starlabs/starfighter: Add Arrow Lake (285H) variant
Tested using `edk2` from `https://github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Ubuntu 24.04 * Manjaro 24 No known issues. https://starlabs.systems/pages/starfighter-specification Change-Id: I75f92cd957c72077460ab4b7ed6b08453f5058d4 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89592 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes
Matt DeVillier
parent
80cf2008a9
commit
36f4341533
22 changed files with 1055 additions and 18 deletions
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@ -25,13 +25,10 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
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select MEMORY_MAPPED_TPM
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select NO_UART_ON_SUPERIO
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select PMC_IPC_ACPI_INTERFACE
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select SOC_INTEL_ALDERLAKE
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select SOC_INTEL_ALDERLAKE_PCH_P
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_COMMON_BLOCK_TCSS
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select SOC_INTEL_CRASHLOG
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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select SOC_INTEL_RAPTORLAKE
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select SPD_READ_BY_WORD
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select SPI_FLASH_WINBOND
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select SYSTEM_TYPE_LAPTOP
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@ -40,12 +37,25 @@ config BOARD_STARLABS_STARFIGHTER_SERIES
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config BOARD_STARLABS_STARFIGHTER_RPL
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select BOARD_STARLABS_STARFIGHTER_SERIES
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select SOC_INTEL_ALDERLAKE
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select SOC_INTEL_ALDERLAKE_PCH_P
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select SOC_INTEL_RAPTORLAKE
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config BOARD_STARLABS_STARFIGHTER_MTL
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select BOARD_STARLABS_STARFIGHTER_SERIES
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select SOC_INTEL_COMMON_BLOCK_VTD
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select SOC_INTEL_METEORLAKE
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select SOC_INTEL_METEORLAKE_U_H
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if BOARD_STARLABS_STARFIGHTER_SERIES
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config BOARD_USES_FIXED_MODE_VBT
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bool
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default y
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config CCD_PORT
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int
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default 3 # TODO
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default 4
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config CONSOLE_SERIAL
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default n if !EDK2_DEBUG
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@ -89,16 +99,18 @@ config MAINBOARD_DIR
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config MAINBOARD_FAMILY
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string
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default "F2" if BOARD_STARLABS_STARFIGHTER_MTL
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default "F1"
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config MAINBOARD_PART_NUMBER
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default "StarFighter Mk II" if BOARD_STARLABS_STARFIGHTER_MTL
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default "StarFighter Mk I"
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "StarFighter"
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config ME_BIN_PATH
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# string
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string
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default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin"
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config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
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@ -107,8 +119,12 @@ config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
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config SOC_INTEL_CSE_SEND_EOP_EARLY
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default n
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config TME_KEY_REGENERATION_ON_WARM_BOOT
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default n
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config TPM_PIRQ
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depends on MAINBOARD_HAS_TPM2
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default 0x3d if BOARD_STARLABS_STARFIGHTER_MTL
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default 0x37
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config UART_FOR_CONSOLE
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@ -121,6 +137,7 @@ config VBOOT
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select VBOOT_VBNV_FLASH
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config VARIANT_DIR
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default "mtl" if BOARD_STARLABS_STARFIGHTER_MTL
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default "rpl"
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endif
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@ -4,3 +4,6 @@ comment "Star Labs StarFighter Series"
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config BOARD_STARLABS_STARFIGHTER_RPL
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bool "Star Labs StarFighter Mk I (i3-1315U, i7-13700H and i9-13900H)"
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config BOARD_STARLABS_STARFIGHTER_MTL
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bool "Star Labs StarFighter Mk II (125H and 285H)"
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@ -64,6 +64,9 @@ static struct sm_obj_form devices = {
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#if CONFIG(DRIVERS_INTEL_USB4_RETIMER)
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&thunderbolt,
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#endif
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#if CONFIG(SOC_INTEL_METEORLAKE)
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&vpu,
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#endif
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NULL
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},
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};
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@ -18,9 +18,13 @@ DefinitionBlock(
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Device (\_SB.PCI0)
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{
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#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
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#if CONFIG(SOC_INTEL_ALDERLAKE)
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#include <soc/intel/alderlake/acpi/southbridge.asl>
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#include <soc/intel/alderlake/acpi/tcss.asl>
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#elif CONFIG(SOC_INTEL_METEORLAKE)
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#include <soc/intel/meteorlake/acpi/southbridge.asl>
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#include <soc/intel/meteorlake/acpi/tcss.asl>
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#endif
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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#include <soc/intel/common/block/acpi/acpi/gna.asl>
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@ -5,6 +5,8 @@
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#include <soc/gpio.h>
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uint8_t get_memory_config_straps(void);
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/*
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* The next set of functions return the gpio table and fill in the number of
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* entries for each table.
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@ -1,7 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <drivers/intel/gma/opregion.h>
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#include <soc/ramstage.h>
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#include <option.h>
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#include <variants.h>
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@ -20,11 +19,3 @@ static void init_mainboard(void *chip_info)
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struct chip_operations mainboard_ops = {
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.init = init_mainboard,
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};
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const char *mainboard_vbt_filename(void)
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{
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if (get_uint_option("display_native_res", 0) == 1)
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return "vbt_native_res.bin";
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return "vbt.bin";
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}
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32
src/mainboard/starlabs/starfighter/spd/32gb-mtl.spd.hex
Normal file
32
src/mainboard/starlabs/starfighter/spd/32gb-mtl.spd.hex
Normal file
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@ -0,0 +1,32 @@
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23 10 13 0E 16 22 B5 08 00 40 00 00 0A 01 00 00
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48 00 0A FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
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04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
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20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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23
src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex
Normal file
23
src/mainboard/starlabs/starfighter/spd/64gb-mtl.spd.hex
Normal file
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@ -0,0 +1,23 @@
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23 10 15 0E 16 2A F9 08 00 40 00 00 09 01 00 00
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48 00 08 FF 92 55 05 00 AA 00 90 A8 90 C0 08 60
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04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00
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20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
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20 20 20 20 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@ -1,5 +1,10 @@
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## SPDX-License-Identifier: GPL-2.0-only
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SPD_SOURCES = 16gb # 13
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SPD_SOURCES += 32gb # 0
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SPD_SOURCES += 64gb # 8
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ifeq ($(CONFIG_BOARD_STARLABS_STARFIGHTER_RPL),y)
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SPD_SOURCES = 16gb # 13
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SPD_SOURCES += 32gb # 0
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SPD_SOURCES += 64gb # 8
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else
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SPD_SOURCES = 32gb-mtl # 13
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SPD_SOURCES += 64gb-mtl # 0
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endif
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15
src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk
Normal file
15
src/mainboard/starlabs/starfighter/variants/mtl/Makefile.mk
Normal file
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@ -0,0 +1,15 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += board_id.c
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romstage-y += romstage.c
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ramstage-y += board_id.c
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ramstage-y += devtree.c
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ramstage-y += gpio.c
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ramstage-y += hda_verb.c
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ramstage-y += ramstage.c
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$(call add_vbt_to_cbfs, vbt_native_res.bin, data_native_res.vbt)
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$(call add_vbt_to_cbfs, vbt_qhd.bin, data_qhd.vbt)
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14
src/mainboard/starlabs/starfighter/variants/mtl/board.fmd
Normal file
14
src/mainboard/starlabs/starfighter/variants/mtl/board.fmd
Normal file
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@ -0,0 +1,14 @@
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FLASH 0x2000000 {
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SI_ALL 0x1000000 {
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SI_DESC 0x4000
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SI_ME 0x80f000
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}
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SI_BIOS 0x1000000 {
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EC@0x0 0x20000
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RW_MRC_CACHE@0x20000 0x10000
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SMMSTORE@0x30000 0x40000
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CONSOLE@0x70000 0x20000
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FMAP@0x90000 0x1000
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COREBOOT(CBFS)
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}
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}
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34
src/mainboard/starlabs/starfighter/variants/mtl/board_id.c
Normal file
34
src/mainboard/starlabs/starfighter/variants/mtl/board_id.c
Normal file
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@ -0,0 +1,34 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <gpio.h>
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#include <variants.h>
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uint8_t get_memory_config_straps(void)
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{
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/*
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* The hardware supports a number of different memory configurations
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* which are selected using four ID bits ID3 (GPP_B05), ID2 (GPP_B06),
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* ID1 (GPP_B07) and ID0 (GPP_B08).
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*
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* +------+-----+-----+-----+-----+
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* | | ID3 | ID2 | ID1 | ID0 |
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* +------+-----+-----+-----+-----+
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* | 32GB | 1 | 0 | 0 | 0 |
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* +------+-----+-----+-----+-----+
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* | 64GB | 1 | 1 | 0 | 1 |
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* +------+-----+-----+-----+-----+
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*
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* We return the value of these bits so that the index into the SPD
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* table can be .spd[] values can be configured correctly in the
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* memory configuration structure.
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*/
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gpio_t spd_id[] = {
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GPP_B05,
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GPP_B06,
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GPP_B07,
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GPP_B08,
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};
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return (uint8_t)gpio_base2_value(spd_id, ARRAY_SIZE(spd_id));
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}
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BIN
src/mainboard/starlabs/starfighter/variants/mtl/data.vbt
Normal file
BIN
src/mainboard/starlabs/starfighter/variants/mtl/data.vbt
Normal file
Binary file not shown.
Binary file not shown.
BIN
src/mainboard/starlabs/starfighter/variants/mtl/data_qhd.vbt
Normal file
BIN
src/mainboard/starlabs/starfighter/variants/mtl/data_qhd.vbt
Normal file
Binary file not shown.
322
src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
Normal file
322
src/mainboard/starlabs/starfighter/variants/mtl/devicetree.cb
Normal file
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@ -0,0 +1,322 @@
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chip soc/intel/meteorlake
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# FSP UPDs
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register "eist_enable" = "true"
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register "pch_pm_energy_report_enable" = "true"
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register "sagv" = "SAGV_ENABLED"
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# Serial I/O
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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}"
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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register "serial_io_uart_mode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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}"
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# Power
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register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS"
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register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S"
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register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
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register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
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device domain 0 on
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device ref igpu on
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chip drivers/gfx/generic
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register "device_count" = "6"
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# [DDIA] eDP
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register "device[0].name" = ""LCD0""
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register "device[0].type" = "panel"
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# [DDIB] HDMI
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register "device[1].name" = ""DD01""
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# [TCP0] Type-C
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register "device[2].name" = ""DD02""
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register "device[2].use_pld" = "true"
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register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
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# [TCP1] Type-C
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register "device[3].name" = ""DD03""
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register "device[3].use_pld" = "true"
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register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
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# [TCP2] N/A
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register "device[4].name" = ""DD04""
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# [TCP3] N/A
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register "device[5].name" = ""DD05""
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device generic 0 on end
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end
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register "ddi_port_A_config" = "1"
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register "ddi_ports_config" = "{
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[DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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}"
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end
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device ref pcie_rp9 on # WiFi
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register "pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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.pcie_rp_aspm = ASPM_L0S_L1,
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.PcieRpL1Substates = L1_SS_L1_2,
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}"
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smbios_slot_desc "SlotTypePciExpressGen3X1"
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"SlotLengthShort"
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"M.2/M 2230"
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"SlotDataBusWidth1X"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B19)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H02)"
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register "srcclk_pin" = "5"
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register "add_acpi_dma_property" = "true"
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register "skip_on_off_support" = "true"
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register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
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register "use_rp_mutex" = "true"
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device generic 0 on end
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end
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end
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device ref pcie_rp10 on # SSD x4
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register "pcie_rp[PCH_RP(10)]" = "{
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.clk_src = 8,
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.clk_req = 8,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
.pcie_rp_aspm = ASPM_L0S_L1,
|
||||
.PcieRpL1Substates = L1_SS_L1_2,
|
||||
}"
|
||||
|
||||
smbios_slot_desc "SlotTypeM2Socket3"
|
||||
"SlotLengthLong"
|
||||
"M.2/M 2280"
|
||||
"SlotDataBusWidth4X"
|
||||
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H07)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
|
||||
register "srcclk_pin" = "8"
|
||||
register "is_storage" = "true"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
register "skip_on_off_support" = "true"
|
||||
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
|
||||
register "use_rp_mutex" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref tbt_pcie_rp0 on end
|
||||
device ref tbt_pcie_rp1 on end
|
||||
device ref gna on end
|
||||
device ref vpu on end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Back USB Type-C""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
|
||||
device ref tcss_usb3_port0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Front USB Type-C""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_dma0 on
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
|
||||
use tcss_usb3_port1 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
|
||||
use tcss_usb3_port2 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref ioe_shared_sram on end
|
||||
device ref xhci on
|
||||
# Motherboard USB 3.0 Type-C Back 7893 mil
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"
|
||||
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
|
||||
# Motherboard USB 3.0 Type-C Front 9557 mil
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"
|
||||
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
|
||||
# Motherboard USB 3.0 Type-A 8916 mil
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
|
||||
# Daughterboard USB 3.0 Type-A 2229 mil
|
||||
register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
|
||||
# Internal Webcam 9070 mil
|
||||
register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
|
||||
# Internal Bluetooth 723 mil
|
||||
register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)"
|
||||
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Back USB Type-C""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 0))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Front USB Type-C""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(0, 1))"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left USB Type-A""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 2)"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Left USB Type-A""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 2)"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Right Rear USB Type-A""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 3)"
|
||||
device ref usb2_port7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Right Rear USB Type-A""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 3)"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Internal Webcam""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 4)"
|
||||
device ref usb2_port5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Internal Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "is_intel_bluetooth" = "true"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B18)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B18)"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 6)"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""STAR0001""
|
||||
register "generic.desc" = ""Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B00_IRQ)"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 2c on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp1 on # SSD x4
|
||||
register "pcie_rp[PCH_RP(1)]" = "{
|
||||
.clk_src = 1,
|
||||
.clk_req = 1,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
.pcie_rp_aspm = ASPM_L0S_L1,
|
||||
.PcieRpL1Substates = L1_SS_L1_2,
|
||||
}"
|
||||
|
||||
smbios_slot_desc "SlotTypeM2Socket3"
|
||||
"SlotLengthLong"
|
||||
"M.2/M 2280"
|
||||
"SlotDataBusWidth4X"
|
||||
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D22)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H00)"
|
||||
register "srcclk_pin" = "1"
|
||||
register "is_storage" = "true"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
register "skip_on_off_support" = "true"
|
||||
register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
|
||||
register "use_rp_mutex" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref uart0 on end
|
||||
device ref soc_espi on
|
||||
register "gen1_dec" = "0x00040069"
|
||||
register "gen2_dec" = "0x00fc0201"
|
||||
register "gen3_dec" = "0x000c0081"
|
||||
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
|
||||
chip ec/starlabs/merlin
|
||||
# Port pair 4Eh/4Fh
|
||||
device pnp 4e.01 off end # Com 1
|
||||
device pnp 4e.02 off end # Com 2
|
||||
device pnp 4e.04 off end # System Wake-Up
|
||||
device pnp 4e.05 off end # PS/2 Mouse
|
||||
device pnp 4e.06 on # PS/2 Keyboard
|
||||
io 0x60 = 0x0060
|
||||
io 0x62 = 0x0064
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 4e.0a off end # Consumer IR
|
||||
device pnp 4e.0f off end # Shared Memory/Flash Interface
|
||||
device pnp 4e.10 off end # RTC-like Timer
|
||||
device pnp 4e.11 off end # Power Management Channel 1
|
||||
device pnp 4e.12 off end # Power Management Channel 2
|
||||
device pnp 4e.13 off end # Serial Peripheral Interface
|
||||
device pnp 4e.14 off end # Platform EC Interface
|
||||
device pnp 4e.17 off end # Power Management Channel 3
|
||||
device pnp 4e.18 off end # Power Management Channel 4
|
||||
device pnp 4e.19 off end # Power Management Channel 5
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port0 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port3 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 1 alias conn1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref hda on
|
||||
subsystemid 0x2014 0x7017
|
||||
register "pch_hda_sdi_enable[0]" = "true"
|
||||
register "pch_hda_dsp_enable" = "true"
|
||||
register "pch_hda_audio_link_hda_enable" = "true"
|
||||
register "pch_hda_idisp_codec_enable" = "true"
|
||||
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
|
||||
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
|
||||
end
|
||||
device ref smbus on end
|
||||
end
|
||||
end
|
||||
68
src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
Normal file
68
src/mainboard/starlabs/starfighter/variants/mtl/devtree.c
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <chip.h>
|
||||
#include <cpu/intel/turbo.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <option.h>
|
||||
#include <static.h>
|
||||
#include <types.h>
|
||||
#include <variants.h>
|
||||
#include <common/powercap.h>
|
||||
|
||||
#define TJ_MAX 110
|
||||
#define TCC(temp) (TJ_MAX - temp)
|
||||
|
||||
void devtree_update(void)
|
||||
{
|
||||
config_t *cfg = config_of_soc();
|
||||
|
||||
struct soc_power_limits_config *soc_conf_20core =
|
||||
&cfg->power_limits_config[MTL_P_682_482_CORE];
|
||||
|
||||
uint8_t performance_scale = 100;
|
||||
|
||||
/* Set PL4 to 1.0C */
|
||||
soc_conf_20core->tdp_pl4 = 65;
|
||||
|
||||
/* Set PL1 to 50% of PL2 */
|
||||
soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl2_override / 2) & ~1;
|
||||
|
||||
/* Scale PL1 & PL2 based on CMOS settings */
|
||||
switch (get_power_profile(PP_POWER_SAVER)) {
|
||||
case PP_POWER_SAVER:
|
||||
performance_scale -= 50;
|
||||
cfg->tcc_offset = TCC(80);
|
||||
break;
|
||||
case PP_BALANCED:
|
||||
performance_scale -= 25;
|
||||
cfg->tcc_offset = TCC(90);
|
||||
break;
|
||||
case PP_PERFORMANCE:
|
||||
/* Use the Intel defaults */
|
||||
cfg->tcc_offset = TCC(100);
|
||||
break;
|
||||
}
|
||||
|
||||
soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl1_override * performance_scale) / 100;
|
||||
soc_conf_20core->tdp_pl2_override = (soc_conf_20core->tdp_pl2_override * performance_scale) / 100;
|
||||
|
||||
/* Enable/Disable Webcam based on CMOS settings */
|
||||
if (get_uint_option("webcam", 1) == 0)
|
||||
cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0;
|
||||
|
||||
/* Enable/Disable Thunderbolt based on CMOS settings */
|
||||
if (get_uint_option("thunderbolt", 1) == 0) {
|
||||
DEV_PTR(tbt_pcie_rp0)->enabled = 0;
|
||||
DEV_PTR(tbt_pcie_rp1)->enabled = 0;
|
||||
DEV_PTR(tcss_dma0)->enabled = 0;
|
||||
}
|
||||
|
||||
/* Enable/Disable GNA based on CMOS settings */
|
||||
if (get_uint_option("gna", 0) == 0)
|
||||
DEV_PTR(gna)->enabled = 0;
|
||||
|
||||
/* Enable/Disable VPU based on CMOS settings */
|
||||
if (get_uint_option("vpu", 0) == 0)
|
||||
DEV_PTR(vpu)->enabled = 0;
|
||||
}
|
||||
260
src/mainboard/starlabs/starfighter/variants/mtl/gpio.c
Normal file
260
src/mainboard/starlabs/starfighter/variants/mtl/gpio.c
Normal file
|
|
@ -0,0 +1,260 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <variants.h>
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
const struct pad_config early_gpio_table[] = {
|
||||
/* Debug Connector */
|
||||
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* RXD */
|
||||
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* TXD */
|
||||
|
||||
/* SMBus */
|
||||
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), /* Clock */
|
||||
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), /* Data */
|
||||
|
||||
/* Board ID */
|
||||
PAD_CFG_GPI_LOCK(GPP_B05, NONE, LOCK_CONFIG),
|
||||
PAD_CFG_GPI_LOCK(GPP_B06, NONE, LOCK_CONFIG),
|
||||
PAD_CFG_GPI_LOCK(GPP_B07, NONE, LOCK_CONFIG),
|
||||
PAD_CFG_GPI_LOCK(GPP_B08, NONE, LOCK_CONFIG),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
const struct pad_config gpio_table[] = {
|
||||
/* General Purpose I/O Deep */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V00, NONE, DEEP, NF1), /* Battery Low */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V01, NONE, DEEP, NF1), /* Charger Connected */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_V03, UP_20K, DEEP, NF1), /* Power Button */
|
||||
PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), /* Sleep S3 */
|
||||
PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), /* Sleep S4 */
|
||||
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), /* Bluetooth Suspend */
|
||||
|
||||
/* eSPI */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A00, UP_20K, DEEP, NF1), /* eSPI IO 0 */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A01, UP_20K, DEEP, NF1), /* eSPI IO 1 */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A02, UP_20K, DEEP, NF1), /* eSPI IO 2 */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A03, UP_20K, DEEP, NF1), /* eSPI IO 3 */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A04, UP_20K, DEEP, NF1), /* eSPI CS 0 */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A05, UP_20K, DEEP, NF1), /* eSPI Clk */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A06, NONE, DEEP, NF1), /* eSPI Reset */
|
||||
|
||||
/* Touchpad */
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* Data */
|
||||
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* Clock */
|
||||
PAD_CFG_GPI_APIC(GPP_B00, NONE, DEEP, LEVEL, INVERT), /* Interrupt */
|
||||
|
||||
/* SSD (CPU)*/
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D20, NONE, PLTRST, NF1), /* Clock Request 8 */
|
||||
PAD_CFG_GPO(GPP_A20, 1, PLTRST), /* Reset */
|
||||
PAD_CFG_GPO(GPP_H07, 1, DEEP), /* Enable */
|
||||
|
||||
/* SSD (PCH) */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C10, NONE, PLTRST, NF1), /* Clock Request 1 */
|
||||
PAD_CFG_GPO(GPP_H00, 1, PLTRST), /* Reset */
|
||||
PAD_CFG_GPO(GPP_D22, 1, DEEP), /* Enable */
|
||||
|
||||
/* Wireless */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_D21, NONE, PLTRST, NF2), /* Clock Request 5 */
|
||||
PAD_CFG_GPO(GPP_H02, 1, PLTRST), /* Reset */
|
||||
PAD_CFG_GPO(GPP_B19, 1, DEEP), /* WiFi RF Kill */
|
||||
PAD_CFG_GPO(GPP_B18, 1, DEEP), /* Bluetooth RF Kill */
|
||||
|
||||
/* Display */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* eDP Hot Plug */
|
||||
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), /* HDMI Hot Plug */
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* HDMI Clock */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* HDMI Data */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_A21, NONE, DEEP, NF1), /* PMC Interrupt */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C06, NONE, DEEP, NF1), /* SML Clock */
|
||||
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_C07, NONE, DEEP, NF1), /* SML Data */
|
||||
|
||||
/* Retimer */
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TBT0 TXD */
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TBT0 RXD */
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TBT1 TXD */
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TBT1 RXD */
|
||||
PAD_CFG_GPO(GPP_B21, 0, DEEP), /* Force Power */
|
||||
|
||||
/* High-Definition Audio */
|
||||
PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1), /* Clock */
|
||||
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), /* Sync */
|
||||
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), /* Data Output */
|
||||
PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), /* Data Input */
|
||||
PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1), /* Reset */
|
||||
|
||||
/* PCH */
|
||||
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* C10 Gate */
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* Platform Reset */
|
||||
PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT), /* Processor Hot */
|
||||
|
||||
/* TPM */
|
||||
PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST), /* Interrupt */
|
||||
|
||||
/* Config Straps [ Low / High ] */
|
||||
PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* Top Swap [ Disabled / Enabled ] */
|
||||
PAD_CFG_GPO(GPP_B04, 0, PLTRST), /* Reboot Support [ Enabled / Disabled ] */
|
||||
PAD_CFG_GPO(GPP_C02, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */
|
||||
PAD_CFG_GPO(GPP_C05, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */
|
||||
PAD_CFG_GPO(GPP_E06, 0, PLTRST), /* JTAG ODT [ Disabled / Enabled ] */
|
||||
PAD_CFG_GPO(GPP_F02, 0, PLTRST), /* M.2 CNVi [ Enabled / Disabled ] */
|
||||
PAD_CFG_GPO(GPP_H01, 0, PLTRST), /* Flash Recovery [ Disabled / Enabled ] */
|
||||
PAD_CFG_GPO(GPP_F20, 0, PLTRST), /* SVID [ Present / Disabled ] */
|
||||
PAD_CFG_GPO(GPP_F21, 0, PLTRST), /* CCD [ BSSB-LS / BALTIC ] */
|
||||
|
||||
PAD_NC(GPP_V02, NONE),
|
||||
PAD_NC(GPP_V06, NONE),
|
||||
PAD_NC(GPP_V07, NONE),
|
||||
PAD_NC(GPP_V09, NONE),
|
||||
PAD_NC(GPP_V10, NONE),
|
||||
PAD_NC(GPP_V11, NONE),
|
||||
PAD_NC(GPP_V12, NONE),
|
||||
PAD_NC(GPP_V13, NONE),
|
||||
PAD_NC(GPP_V14, NONE),
|
||||
PAD_NC(GPP_V15, NONE),
|
||||
PAD_NC(GPP_V16, NONE),
|
||||
PAD_NC(GPP_V17, NONE),
|
||||
PAD_NC(GPP_V18, NONE),
|
||||
PAD_NC(GPP_V19, NONE),
|
||||
PAD_NC(GPP_V20, NONE),
|
||||
PAD_NC(GPP_V21, NONE),
|
||||
PAD_NC(GPP_V22, NONE),
|
||||
PAD_NC(GPP_V23, NONE),
|
||||
|
||||
PAD_NC(GPP_C03, NONE),
|
||||
PAD_NC(GPP_C04, NONE),
|
||||
PAD_NC(GPP_C08, NONE),
|
||||
PAD_NC(GPP_C09, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_NC(GPP_C14, NONE),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_NC(GPP_C22, NONE),
|
||||
PAD_NC(GPP_C23, NONE),
|
||||
|
||||
PAD_NC(GPP_A07, NONE),
|
||||
PAD_NC(GPP_A08, NONE),
|
||||
PAD_NC(GPP_A09, NONE),
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
PAD_NC(GPP_A12, NONE),
|
||||
PAD_NC(GPP_A13, NONE),
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
PAD_NC(GPP_A18, NONE),
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
PAD_NC(GPP_A23, NONE),
|
||||
|
||||
PAD_NC(GPP_E00, NONE),
|
||||
PAD_NC(GPP_E01, NONE),
|
||||
PAD_NC(GPP_E02, NONE),
|
||||
PAD_NC(GPP_E03, NONE),
|
||||
PAD_NC(GPP_E04, NONE),
|
||||
PAD_NC(GPP_E05, NONE),
|
||||
PAD_NC(GPP_E07, NONE),
|
||||
PAD_NC(GPP_E08, NONE),
|
||||
PAD_NC(GPP_E09, NONE),
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
PAD_NC(GPP_E15, NONE),
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
PAD_NC(GPP_E18, NONE),
|
||||
PAD_NC(GPP_E19, NONE),
|
||||
PAD_NC(GPP_E20, NONE),
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
|
||||
PAD_NC(GPP_H03, NONE),
|
||||
PAD_NC(GPP_H04, NONE),
|
||||
PAD_NC(GPP_H05, NONE),
|
||||
PAD_NC(GPP_H06, NONE),
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
PAD_NC(GPP_H18, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
|
||||
PAD_NC(GPP_F00, NONE),
|
||||
PAD_NC(GPP_F01, NONE),
|
||||
PAD_NC(GPP_F03, NONE),
|
||||
PAD_NC(GPP_F04, NONE),
|
||||
PAD_NC(GPP_F05, NONE),
|
||||
PAD_NC(GPP_F06, NONE),
|
||||
PAD_NC(GPP_F07, NONE),
|
||||
PAD_NC(GPP_F08, NONE),
|
||||
PAD_NC(GPP_F09, NONE),
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_NC(GPP_F17, NONE),
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
|
||||
PAD_NC(GPP_S00, NONE),
|
||||
PAD_NC(GPP_S01, NONE),
|
||||
PAD_NC(GPP_S02, NONE),
|
||||
PAD_NC(GPP_S03, NONE),
|
||||
PAD_NC(GPP_S04, NONE),
|
||||
PAD_NC(GPP_S05, NONE),
|
||||
PAD_NC(GPP_S06, NONE),
|
||||
PAD_NC(GPP_S07, NONE),
|
||||
|
||||
PAD_NC(GPP_B01, NONE),
|
||||
PAD_NC(GPP_B02, NONE),
|
||||
PAD_NC(GPP_B03, NONE),
|
||||
PAD_NC(GPP_B09, NONE),
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
PAD_NC(GPP_B11, NONE),
|
||||
PAD_NC(GPP_B12, NONE),
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
PAD_NC(GPP_B23, NONE),
|
||||
|
||||
PAD_NC(GPP_D00, NONE),
|
||||
PAD_NC(GPP_D01, NONE),
|
||||
PAD_NC(GPP_D02, NONE),
|
||||
PAD_NC(GPP_D03, NONE),
|
||||
PAD_NC(GPP_D04, NONE),
|
||||
PAD_NC(GPP_D05, NONE),
|
||||
PAD_NC(GPP_D06, NONE),
|
||||
PAD_NC(GPP_D07, NONE),
|
||||
PAD_NC(GPP_D08, NONE),
|
||||
PAD_NC(GPP_D09, NONE),
|
||||
PAD_NC(GPP_D14, NONE),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
PAD_NC(GPP_D23, NONE),
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
105
src/mainboard/starlabs/starfighter/variants/mtl/hda_verb.c
Normal file
105
src/mainboard/starlabs/starfighter/variants/mtl/hda_verb.c
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
#include <device/azalia_codec/realtek.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0235, /* Codec Vendor / Device ID: Realtek ALC235 */
|
||||
0x20147017, /* Subsystem ID */
|
||||
18, /* Number of verb entries */
|
||||
|
||||
/* Reset Codec First */
|
||||
AZALIA_RESET(0x1),
|
||||
|
||||
/* HDA Codec Subsystem ID */
|
||||
AZALIA_SUBVENDOR(0, 0x20147017),
|
||||
|
||||
/* Pin Widget Verb-table */
|
||||
AZALIA_PIN_CFG(0, ALC269_DMIC12, AZALIA_PIN_DESC(
|
||||
AZALIA_INTEGRATED,
|
||||
AZALIA_MOBILE_LID_INSIDE,
|
||||
AZALIA_MIC_IN,
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_NO_JACK_PRESENCE_DETECT,
|
||||
3,
|
||||
0
|
||||
)),
|
||||
AZALIA_PIN_CFG(0, ALC269_MIC2, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
|
||||
AZALIA_MIC_IN,
|
||||
AZALIA_STEREO_MONO_1_8,
|
||||
AZALIA_BLACK,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
4,
|
||||
0
|
||||
)),
|
||||
/* Internal speakers are connected to LINE2 and external amps */
|
||||
AZALIA_PIN_CFG(0, ALC269_LINE2, AZALIA_PIN_DESC(
|
||||
AZALIA_INTEGRATED,
|
||||
AZALIA_INTERNAL | AZALIA_FRONT,
|
||||
AZALIA_SPEAKER,
|
||||
AZALIA_OTHER_ANALOG,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_NO_JACK_PRESENCE_DETECT,
|
||||
1,
|
||||
0
|
||||
)),
|
||||
AZALIA_PIN_CFG(0, ALC269_VB_HP_OUT, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
|
||||
AZALIA_HP_OUT,
|
||||
AZALIA_STEREO_MONO_1_8,
|
||||
AZALIA_BLACK,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
2,
|
||||
0
|
||||
)),
|
||||
AZALIA_PIN_CFG(0, ALC269_PC_BEEP, AZALIA_PIN_DESC(
|
||||
AZALIA_NC,
|
||||
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_GEOLOCATION_NA,
|
||||
AZALIA_LINE_IN,
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_PINK,
|
||||
0xa,
|
||||
4,
|
||||
5
|
||||
)),
|
||||
AZALIA_PIN_CFG(0, 0x20, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, ALC269_MONO, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, ALC269_MIC1, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, ALC269_SPEAKERS, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, ALC269_LINE1, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, ALC269_SPDIF_OUT, AZALIA_PIN_CFG_NC(0)),
|
||||
|
||||
0x05750003,
|
||||
0x057486a6,
|
||||
0x02050034,
|
||||
0x02048204,
|
||||
|
||||
0x0205001b,
|
||||
0x02040a0b,
|
||||
0x02050046,
|
||||
0x02040004,
|
||||
|
||||
0x02050008,
|
||||
0x02046a0c,
|
||||
0x02050040,
|
||||
0x02041800,
|
||||
|
||||
0x02050037,
|
||||
0x02044a06,
|
||||
0x0205004c,
|
||||
0x02044803,
|
||||
|
||||
0x02050019,
|
||||
0x02040a10,
|
||||
0x02050035,
|
||||
0x020488aa,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
24
src/mainboard/starlabs/starfighter/variants/mtl/ramstage.c
Normal file
24
src/mainboard/starlabs/starfighter/variants/mtl/ramstage.c
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <option.h>
|
||||
#include <drivers/intel/gma/opregion.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <variants.h>
|
||||
#include <common/pin_mux.h>
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
|
||||
{
|
||||
configure_pin_mux(supd);
|
||||
supd->TcNotifyIgd = 2; // Auto
|
||||
}
|
||||
|
||||
const char *mainboard_vbt_filename(void)
|
||||
{
|
||||
if (get_uint_option("display_native_res", 0) == 1)
|
||||
return "vbt_native_res.bin";
|
||||
|
||||
|
||||
if (get_memory_config_straps() == 13)
|
||||
return "vbt_qhd.bin";
|
||||
return "vbt.bin";
|
||||
}
|
||||
106
src/mainboard/starlabs/starfighter/variants/mtl/romstage.c
Normal file
106
src/mainboard/starlabs/starfighter/variants/mtl/romstage.c
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <option.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <types.h>
|
||||
#include <variants.h>
|
||||
|
||||
static uint8_t strap_to_cbfs_index(uint8_t strap)
|
||||
{
|
||||
switch (strap) {
|
||||
case 13: // 32GB
|
||||
return 0;
|
||||
default: // 64GB
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mb_cfg mem_config = {
|
||||
.type = MEM_TYPE_LP5X,
|
||||
|
||||
.lpx_dq_map = {
|
||||
.ddr0 = {
|
||||
.dq0 = { 8, 11, 10, 9, 15, 12, 13, 14 },
|
||||
.dq1 = { 4, 7, 5, 6, 3, 1, 2, 0 },
|
||||
},
|
||||
.ddr1 = {
|
||||
.dq0 = { 2, 0, 3, 1, 4, 6, 7, 5 },
|
||||
.dq1 = { 13, 10, 12, 15, 11, 8, 9, 14 },
|
||||
},
|
||||
.ddr2 = {
|
||||
.dq0 = { 0, 3, 1, 2, 4, 7, 6, 5 },
|
||||
.dq1 = { 8, 15, 9, 12, 10, 11, 14, 13 },
|
||||
},
|
||||
.ddr3 = {
|
||||
.dq0 = { 13, 10, 8, 9, 14, 11, 15, 12 },
|
||||
.dq1 = { 1, 6, 4, 7, 0, 5, 2, 3 },
|
||||
},
|
||||
.ddr4 = {
|
||||
.dq0 = { 10, 11, 9, 12, 13, 14, 15, 8 },
|
||||
.dq1 = { 6, 7, 4, 5, 1, 0, 3, 2 },
|
||||
},
|
||||
.ddr5 = {
|
||||
.dq0 = { 0, 5, 3, 6, 1, 4, 2, 7 },
|
||||
.dq1 = { 8, 11, 10, 9, 15, 14, 13, 12 },
|
||||
},
|
||||
.ddr6 = {
|
||||
.dq0 = { 1, 3, 0, 2, 6, 5, 7, 4 },
|
||||
.dq1 = { 13, 15, 14, 12, 11, 10, 8, 9 },
|
||||
},
|
||||
.ddr7 = {
|
||||
.dq0 = { 10, 9, 11, 8, 12, 15, 14, 13 },
|
||||
.dq1 = { 6, 4, 7, 5, 2, 1, 0, 3 },
|
||||
},
|
||||
},
|
||||
|
||||
/* DQS CPU<>DRAM map */
|
||||
.lpx_dqs_map = {
|
||||
.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr7 = { .dqs0 = 1, .dqs1 = 0 },
|
||||
},
|
||||
|
||||
.ect = true,
|
||||
|
||||
.LpDdrDqDqsReTraining = 1,
|
||||
|
||||
.UserBd = BOARD_TYPE_ULT_ULX,
|
||||
.lp5x_config = {
|
||||
.ccc_config = 0x66,
|
||||
}
|
||||
};
|
||||
|
||||
const bool half_populated = false;
|
||||
|
||||
const struct mem_spd lpddr5_spd_info = {
|
||||
.topo = MEM_TOPO_MEMORY_DOWN,
|
||||
.cbfs_index = strap_to_cbfs_index(get_memory_config_straps()),
|
||||
};
|
||||
|
||||
memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated);
|
||||
|
||||
const uint8_t vtd = get_uint_option("vtd", 1);
|
||||
mupd->FspmConfig.VtdDisable = !vtd;
|
||||
|
||||
/* Enable/Disable Wireless (RP09) based on CMOS settings */
|
||||
if (get_uint_option("wireless", 1) == 0)
|
||||
mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8);
|
||||
|
||||
/* Enable/Disable Thunderbolt based on CMOS settings */
|
||||
if (get_uint_option("thunderbolt", 1) == 0) {
|
||||
mupd->FspmConfig.TcssDma0En = 0;
|
||||
mupd->FspmConfig.TcssItbtPcie0En = 0;
|
||||
mupd->FspmConfig.TcssXhciEn = 0;
|
||||
}
|
||||
|
||||
mupd->FspmConfig.PchHdaSubSystemIds = 0x20147017;
|
||||
mupd->FspmConfig.PsysPmax = 0;
|
||||
};
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <option.h>
|
||||
#include <drivers/intel/gma/opregion.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <common/pin_mux.h>
|
||||
|
||||
|
|
@ -11,3 +12,11 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *supd)
|
|||
if (get_uint_option("thunderbolt", 1) == 0)
|
||||
supd->UsbTcPortEn = 0;
|
||||
}
|
||||
|
||||
const char *mainboard_vbt_filename(void)
|
||||
{
|
||||
if (get_uint_option("display_native_res", 0) == 1)
|
||||
return "vbt_native_res.bin";
|
||||
|
||||
return "vbt.bin";
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue