mb/siemens/mc_ehl6: Send POST codes to NC FPGA via PCI

Enable the feature to send POST codes to the NC FPGA via PCI. This
allows the POST codes to be visible on the embedded 7-segment display
during coreboot runtime.
Further sort switches in alphabetical order.

TEST=Build and boot mc_ehl6. Verify that the POST Codes are
correctly displayed on the embedded 7-segment display.

Change-Id: Ie7e4961c0345312126eb2000c2934e33fce3b584
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Kconfig

@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_ETH_PHY_M88E1512
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
+	select NC_FPGA_POST_CODE
 	select TPM_MEASURED_BOOT
 	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
 
@@ -21,4 +22,19 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
+config EARLY_PCI_BRIDGE_DEVICE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x1c
+
+config EARLY_PCI_BRIDGE_FUNCTION
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x0
+
+config EARLY_PCI_MMIO_BASE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0xfe800000
+
 endif # BOARD_SIEMENS_MC_EHL6

src/mainboard/siemens/mc_ehl/variants/mc_ehl6/Makefile.mk

@@ -4,3 +4,5 @@ bootblock-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
 ramstage-y += mainboard.c
+
+all-$(CONFIG_NC_FPGA_POST_CODE) += post.c

src/mainboard/siemens/mc_ehl/variants/mc_ehl6/post.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <nc_fpga.h>
+#include <types.h>
+
+void mainboard_post(uint8_t value)
+{
+	nc_fpga_post(value);
+}