mb/siemens/mc_ehl6: Activate SATA interface port 1

Activate SATA interface port 1 for mass storage connection on mc_ehl6
mainboard.
Function of SATA_LED_N and M.2_SSD_SATA_DEVSLP_1 are not used.

TEST=Check mass storage in running OS.

Change-Id: I34ca0d71a04c4338e35bcf9ede4ccef41efab01e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Uwe Poeche 2025-07-15 13:23:32 +02:00 committed by Matt DeVillier
commit 760c3f6abc
2 changed files with 9 additions and 4 deletions

View file

@ -75,7 +75,13 @@ chip soc/intel/elkhartlake
register "PciePtm[4]" = "true"
register "PciePtm[6]" = "true"
# Storage (SDCARD/EMMC) related UPDs
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "0"
register "SataPortsSSD[1]" = "1"
register "SataSpeed" = "SATA_GEN2"
register "ScsEmmcHs400Enabled" = "0"
register "ScsEmmcDdr50Enabled" = "1"
register "SdCardPowerEnableActiveHigh" = "1"
@ -119,7 +125,6 @@ chip soc/intel/elkhartlake
register "PchTsnGbeSgmiiEnable" = "1"
register "PseDmaOwn[0]" = "Host_Owned"
# FIVR related settings
register "fivr" = "{
.fivr_config_en = true,
@ -178,6 +183,8 @@ chip soc/intel/elkhartlake
device pci 16.0 hidden end # Management Engine Interface 1
device pci 17.0 on end # SATA
device pci 19.0 on # I2C4
# Add dummy I2C device to limit BUS speed to 100 kHz in OS
chip drivers/i2c/generic

View file

@ -110,8 +110,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_F20, 0, DEEP), /* LED_BIOS_DONE */
/* Community 4 - GpioGroup GPP_E */
PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), /* M.2_SSD_SATA_DEVSLP_1 */
PAD_NC(GPP_E15, NONE), /* Not connected */
PAD_NC(GPP_E16, NONE), /* Not connected */
PAD_NC(GPP_E18, NONE), /* Not connected */