mb/siemens/mc_ehl6: Activate SATA interface port 1
Activate SATA interface port 1 for mass storage connection on mc_ehl6 mainboard. Function of SATA_LED_N and M.2_SSD_SATA_DEVSLP_1 are not used. TEST=Check mass storage in running OS. Change-Id: I34ca0d71a04c4338e35bcf9ede4ccef41efab01e Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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2 changed files with 9 additions and 4 deletions
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@ -75,7 +75,13 @@ chip soc/intel/elkhartlake
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register "PciePtm[4]" = "true"
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register "PciePtm[6]" = "true"
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# Storage (SDCARD/EMMC) related UPDs
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# Storage (SATA/SDCARD/EMMC) related UPDs
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register "SataSalpSupport" = "0"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsDevSlp[1]" = "0"
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register "SataPortsSSD[1]" = "1"
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register "SataSpeed" = "SATA_GEN2"
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsEmmcDdr50Enabled" = "1"
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register "SdCardPowerEnableActiveHigh" = "1"
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@ -119,7 +125,6 @@ chip soc/intel/elkhartlake
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register "PchTsnGbeSgmiiEnable" = "1"
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register "PseDmaOwn[0]" = "Host_Owned"
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# FIVR related settings
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register "fivr" = "{
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.fivr_config_en = true,
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@ -178,6 +183,8 @@ chip soc/intel/elkhartlake
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device pci 16.0 hidden end # Management Engine Interface 1
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device pci 17.0 on end # SATA
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device pci 19.0 on # I2C4
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# Add dummy I2C device to limit BUS speed to 100 kHz in OS
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chip drivers/i2c/generic
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@ -110,8 +110,6 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPO(GPP_F20, 0, DEEP), /* LED_BIOS_DONE */
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/* Community 4 - GpioGroup GPP_E */
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PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), /* M.2_SSD_SATA_DEVSLP_1 */
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PAD_NC(GPP_E15, NONE), /* Not connected */
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PAD_NC(GPP_E16, NONE), /* Not connected */
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PAD_NC(GPP_E18, NONE), /* Not connected */
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