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mb/siemens/mc_ehl6: Limit PCIe RP7 speed to Gen2

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Configure PCIe root port 7 to operate at PCIe Gen2 speed to fulfill
mainboard constraints regarding signal integrity.

TEST=Check resulting transfer rate in OS via
`lspci -vv -s 06:00.0 | grep LnkSta`.
Output shows `LnkSta: Speed 5GT/s (downgraded), Width x2`

Change-Id: I7cb86f04675a850bf3c0a3e8af2436d929d5768b
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
This commit is contained in:
Uwe Poeche 2025-09-29 06:47:09 +02:00 • committed by Matt DeVillier
commit fceb033372
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
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@ -75,6 +75,9 @@ chip soc/intel/elkhartlake
register "PciePtm[4]" = "true"
register "PciePtm[6]" = "true"
# Determine PCIe root port speed
register "PcieRpPcieSpeed[6]" = "2"
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
register "SataPortsEnable[1]" = "1"