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mb/siemens/mc_rpl1: Enable IBECC

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Enable In-band ECC (IBECC) for mc_rpl1. IBECC provides memory error
detection and correction capabilities without requiring ECC memory
modules.

TEST=Inject correctable Error and verify IBECC detection and correction
through system logs. Testing based on Intel Doc. #751401

Change-Id: Ibf2a61bf425a51762fa8bb1cfe7b6f57edd3cfb5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
This commit is contained in:
Kilian Krause 2025-11-21 10:41:07 +01:00 • committed by Matt DeVillier
commit f1d1c825dc
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
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@ -17,6 +17,12 @@ chip soc/intel/alderlake
[1] = 1,
}"
# Enable IBECC for the complete memory
register "ibecc" = "{
.enable = 1,
.mode = IBECC_MODE_ALL
}"
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Port2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB