Refine dptx_get_edid function to read extension edid to bring up 2.8k
120hz OLED panel.
BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
EQ training pass
Change-Id: If35782950ae02d892ea697580fa4991595c21533
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86779
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Controller2 and controller3 are disabled, so remove them from source
code.
BRANCH=rauru
BUG=b:389026545
TEST=Boot up to kernel
Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu@mediatek.corp-partner.google.com>
Change-Id: I69c1e76e7de544fd4e24e8e94e4f676de783e205
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
HWRot (Hardware Root of trust) is not used, so we disable its clocks to
save power. This patch is a subitem of Vcore power consumption
improvement. The whole work improves SoC power consumption from 120mW to
90mW in suspend.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK & Suspend/Resume passed
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I25e607e8e8b2d52608d279e1862f423ca50aab6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86553
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB.
BUG=b:379008996
BRANCH=none
TEST=booted successfully
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86538
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Move gpio_get_eint_reg() and gpio_calc_eint_pos_bit() to common code
to avoid redundant definitions for other platforms such as MT8189.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Id21f627a49f730f3a0db786a148f81806aeba287
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86541
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To fix the SPMI-P glitch, set the mt6316 deglitch time from 2ns to 4ns.
Additionally, a hardware solution of SPMI damping to 0 ohm is needed.
BRANCH=rauru
TEST=Build passed and booted successfully. 10 platforms have passed CPU
stress tests over multiple iterations.
BUG=b:386438329
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: I77bd50cc6c25d6dcded57d9d65d92a0dd19c3c86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Knox Chiou <knoxchiou@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Configure PMIC register 0x50c bit0 which decides whether to use external
xtal. This bit of mt6685 should be set to 1, to disable external xtal.
BRANCH=rauru
BUG=b:395485005
TEST=emerge-rauru coreboot chromeos-bootimage, remove battery and
charger, then insert battery and charge, RTC boots normally.
Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Change-Id: Iea44f13af030f24c02993dd43a35a9d8b4f72179
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86353
Reviewed-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The tvdpll3 cannot be disabled during suspend because of the enable
operation, so we remove the enable operation. Hardware can now
automatically enable and disable tvdpll3 based on the clock demand of
its downstream.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK, Suspend/Resume OK and FW screen shown OK, with MMinfra
kernel/vcp patch, mminfra can be turned off to reduce power consumption.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86343
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
As MT8196 won't be able to boot up without mtk_fsp_romstage.elf and
mtk_fsp_ramstage.elf, ensure their presence in build time.
Change-Id: I668319ae1f63818e324002e7ae4d888479edb9cf
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Correct MMinfra vote register to fix MMinfra power off failure during
suspend.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK and Suspend/Resume OK, with MMinfra kernel/vcp patch,
mminfra can be turned off to reduce power consumption by 50mW.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I7c23c3c53c68b0de85d8b6189b685de7f8398e8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86342
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set
to a maximum value of 16mA. Additionally, a hardware solution of
external pull-down is also required.
BRANCH=rauru
TEST=Build passed and booted successfully. The platform remained idle
for approximately 20 hours without hang.
BUG=b:383634290
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Measure mtk_fsp_load_and_run() execution time. This info helps AP boot
time analysis. The logs show as below.
[INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_romstage at phase 0x30 in 0 msecs
[INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_ramstage at phase 0x50 in 41 msecs
BUG=none
BRANCH=rauru
TEST=cbmem -1|grep "mtk_fsp_load_and_run"
Change-Id: I61706952bef4590c5bfd09707a08a4f1a25fbda2
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Set mcufw_reserved region to non-cacheable and remove cache operation in
dvfs.c.
TEST=Build pass, boot ok.
Check MMU List by CVD (Codeviser):
0x00113000--0x00123FFF = I:non-cacheable O:non-cacheable
BUG=b:390334489
Change-Id: I886effd59006e5ad4bfe5bdbc14f057520304835
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86159
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Adjust the allocated region size for mcufw_reserved from 52K to 68K.
TEST=Build pass.
BUG=b:390334489
Change-Id: I1c17c1492d5568f4d51ff45e1fb90e067eae5cb1
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
We should be writing to the address of reg[i], instead of the address
whose value is reg[i].
Change-Id: I4fb78f974155725a91aad3a5450733d24b57af15
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
If the modem is not completely disabled, it will cause issues with
suspend to RAM. Update the condition check in MD1_PWR_STA and increased
the MAX_RETRY_COUNT from 200 to 4000 to make sure that the modem has
sufficient time to completely disable before proceeding.
TEST=Measure the power and ensure that the DRAM enters self-refresh
mode.
BUG=b:377628718
Change-Id: I6e915d26e5b3caee36f4726bc2fc1c53cfc17bfc
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add eDP driver to adjust training flow and turn off PHY power before PHY
configuration to prevent potential link training failures.
DISP_DVO is a highly advanced variant of DP_INTF block for eDP or HDMI
or simply digital video output. DISP represents “display”, while DVO is
the abbreviation of “digital video output”. This version of DISP_DVO is
mainly designed for eDP1.5 protocol.
TEST=check edp training pass and show log:
EQ training pass
BUG=b:343351631
Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85949
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the initialization code for CPU Dynamic Voltage and Frequency
Scaling (DVFS) for MCUPM.
TEST=Build pass.
BUG=b:317009620
Change-Id: I92b7c57ad8c3d9e9954f02a08954939f45c5e2c2
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86041
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As the mtk_pwrsel.{c,h} files are already under the soc/mediatek
directory, drop the file name prefix "mtk_" from them.
BUG=b:317009620
TEST=none
Change-Id: I28131d44067c33b5d8682a85cc8a73fc42604de3
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86059
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EINT event mask register is used to mask EINT wakeup source. All wakeup
sources are masked by default. Since most MediaTek SoCs do not have this
design, we can't modify the kernel EINT upstream driver to solve the
issue "Can't wake using power button (cros_ec) or touchpad". So we add a
driver here to unmask all wakeup sources.
TEST=write eint data successfully.
BUG=b:317009620
Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3
Signed-off-by: Chhao Chang <ot_chhao.chang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84025
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
When writing key_protect_setting to PMIC, PMIC expects receiving 1 byte
per write. PMIC would receive unexpected zero byte if using
mt6685_write16. Fix the write operation by using mt6685_write8.
TEST=Build pass.
BUG=b:388666377
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86035
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the issue where the DUT cannot power on during S5. When writing
key_protect_setting to PMIC, PMIC expects receiving 1 byte per write.
PMIC would receive unexpected zero byte if using mt6363_write16. Fix the
write operation by using mt6363_write8.
TEST=Build pass, DUT can power on during S5.
BUG=b:388666377
Change-Id: I0a7c0d2fa1f93a55731b4b58923d6f80a4c4be89
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86034
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction
ACK from SPM: 0, non-SPM: 0x1.
In MT8196, SPM has masked all the DDR requests, so this setting should
be set to non-SPM whenever mminfra is powering on. Otherwise, GCE will
hang when accessing DRAM.
BUG=b:379039600
TEST=boot up ok, GCE can access DRAM continuously
Change-Id: I30309b0426f803e28858eb15652a649927f94c7e
Signed-off-by: Jason-jh Lin <jason-jh.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
In the current eDP initialization flow, eDP is configured and enabled
before display data pipe (DDP) initialization. The init flow is wrong,
because eDP should be enabled only after DDP is correctly set up. The
wrong flow may lead to garbage display between enabling eDP and
configuring DDP.
To fix the problem, the dptx_video_enable(true) call needs to be moved
after mtk_ddp_mode_set(). Introduce a new API mtk_edp_enable() for eDP
enablement, to be separated from the existing mtk_edp_init(). The fixed
eDP init flow is: mtk_edp_init -> mtk_ddp_mode_set -> mtk_edp_enable.
Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86028
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Unlike MT8186/MT8188/MT8192/MT8195, MT8196 has 5 EINT base registers,
each with a different number of EINT bits. In preparation for the
upcoming MT8196 EINT unmasking support, replace the `eint_event_reg`
struct (which has a hardcoded register number) with an array
`eint_event` to specify the EINT base register(s).
BUG=none
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I86fd3109c9ff72f33b9fea45587d012b003a34ba
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86033
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Load MCUPM firmware and boot up MCUPM in ramstage.
It takes 54 ms to load mcupm.bin.
coreboot logs:
CBFS: Found 'mcupm.bin' @0x37a80 size 0xdbda in mcache @0xfffdd308
mtk_init_mcu: Loaded (and reset) mcupm.bin in 54 msecs (486931 bytes)
TEST=Build pass and we can see the mcupm logs after reset releases.
BUG=b:317009620
Change-Id: I223f245d384f32d54f6170a28b29573638f77296
Signed-off-by: Agogo Huang <agogo.huang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
mt6373_init_pmif_arb() needs to be initialized for SD card to control
the regulator.
TEST=emrege-rauru coreboot
TEST=The assertion is gone on Rauru during normal boot.
Change-Id: I7e3265bb62a6c78d44e2c756be9a020a49a03056
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85969
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Return to the caller immediately if pmif_arb has been initiailized. In
this way, we can skip unnecessary check and reduce the access to the
PMIF register.
TEST=emerge-geralt coreboot && emerge-rauru coreboot
Change-Id: Id1d11f8b238855edb393d77151159792e7716d22
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The function rtc_get_frequency_meter() already uses the wait_us() macro,
so the stopwatch variable "sw" is not needed.
Change-Id: I7e282b6ce881f4e8f9d5e1c92803fda363fe28d7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
MT8196 uses new RC mode with clk_buf driver, and needs srclken_rc to
send PMRC_EN. PMRC_EN will collect the requirements of all users,
such as MD, GPS, PCIE, NFC.
TEST=Build pass.
BUG=b:317009620
Signed-off-by: ot_song fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85842
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
MT8196 uses MT6685 clk_buf, and will use new RC mode with srclken_rc.
The clk_buf will provide several 26M clocks, and these clocks can be
independently turned on. RC mode will determine which clocks to be
turned on based on users' requests, which is collected into PMRC_EN
register by srclken_rc.
TEST=Build pass.
BUG=b:317009620
Signed-off-by: ot_song fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
With CB:85918 and CB:85930, we can clean up the TODO in mtk_dp_mask.
Follow DP Phy APIs to use `assert` for the param examination.
TEST=verified on Ciri and Navi
Change-Id: I94e6ad36d190d773876cbb43eb4ebe17164f3c92
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85931
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
