Yu-Ping Wu b229c120f7 soc/mediatek: Allow specifying multiple EINT base registers ... Unlike MT8186/MT8188/MT8192/MT8195, MT8196 has 5 EINT base registers, each with a different number of EINT bits. In preparation for the upcoming MT8196 EINT unmasking support, replace the `eint_event_reg` struct (which has a hardcoded register number) with an array `eint_event` to specify the EINT base register(s). BUG=none TEST=emerge-geralt coreboot BRANCH=none Change-Id: I86fd3109c9ff72f33b9fea45587d012b003a34ba Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86033 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-01-18 13:09:40 +00:00
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common	soc/mediatek: Allow specifying multiple EINT base registers	2025-01-18 13:09:40 +00:00
mt8173	soc/mediatek/common: Rename GPT_MHZ to TIMER_MHZ for readability	2024-12-21 16:09:23 +00:00
mt8183	tree: Remove unused <assert.h>	2024-11-19 00:40:04 +00:00
mt8186	soc/mediatek: Allow specifying multiple EINT base registers	2025-01-18 13:09:40 +00:00
mt8188	soc/mediatek: Allow specifying multiple EINT base registers	2025-01-18 13:09:40 +00:00
mt8189	soc/mediatek/mt8189: Enable timer compensation v2.5	2024-12-24 11:22:38 +00:00
mt8192	soc/mediatek: Allow specifying multiple EINT base registers	2025-01-18 13:09:40 +00:00
mt8195	soc/mediatek: Allow specifying multiple EINT base registers	2025-01-18 13:09:40 +00:00
mt8196	soc/mediatek/mt8196: Initialize MCUPM	2025-01-18 04:32:13 +00:00