coreboot/src/soc/mediatek
Jarried Lin 69c2d75d52 soc/mediatek/mt8196: Add mtk-fsp loader in ramstage
MediaTek firmware support package (mtk-fsp) contains romstage and
ramstage blobs. Add support for the ramstage blob, which includes:
- UFS mphy settings.
- DPAC (Device Access Permission Control) settings.
- MMinfra (Multimedia Infrastrucutre) settings.
- SMPU (Security Memory Protection Unit) settings.
- Advanced CPU frequency control.

BUG=b:373797027
TEST=build pass, boot ok.
Load and run mtk_fsp with following logs:
[INFO ] CBFS: Found 'fallback/mtk_fsp_ramstage' @0xfca00 size 0x263d in
        mcache @0xfffdd5a0
[DEBUG] read SPI 0x4fea88 0x263d: 773 us, 12663 KB/s, 101.304 Mbps
[INFO ] VB2:vb2_digest_init() 9789 bytes, hash algo 2, HW acceleration
        enabled
[INFO ] _start: MediaTek FSP_RAMSTAGE interface version: 1.0
[INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_ramstage at phase
        0x50 done

Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86013
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-01-18 13:10:56 +00:00
..
common soc/mediatek/mt8196: Add mtk-fsp loader in ramstage 2025-01-18 13:10:56 +00:00
mt8173 soc/mediatek/common: Rename GPT_MHZ to TIMER_MHZ for readability 2024-12-21 16:09:23 +00:00
mt8183 tree: Remove unused <assert.h> 2024-11-19 00:40:04 +00:00
mt8186 soc/mediatek: Allow specifying multiple EINT base registers 2025-01-18 13:09:40 +00:00
mt8188 soc/mediatek: Allow specifying multiple EINT base registers 2025-01-18 13:09:40 +00:00
mt8189 soc/mediatek/mt8189: Enable timer compensation v2.5 2024-12-24 11:22:38 +00:00
mt8192 soc/mediatek: Allow specifying multiple EINT base registers 2025-01-18 13:09:40 +00:00
mt8195 soc/mediatek: Allow specifying multiple EINT base registers 2025-01-18 13:09:40 +00:00
mt8196 soc/mediatek/mt8196: Add mtk-fsp loader in ramstage 2025-01-18 13:10:56 +00:00