soc/mediatek/mt8196: Add DVFS driver

Add the initialization code for CPU Dynamic Voltage and Frequency
Scaling (DVFS) for MCUPM.

TEST=Build pass.
BUG=b:317009620

Change-Id: I92b7c57ad8c3d9e9954f02a08954939f45c5e2c2
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86041
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/mt8196/Makefile.mk

@@ -28,6 +28,7 @@ romstage-y += ../common/cbmem.c
 romstage-y += clkbuf_ctl.c
 romstage-y += ../common/dram_init.c
 romstage-y += ../common/dramc_param.c
+romstage-y += dvfs.c
 romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c
 romstage-y += ../common/emi.c
 romstage-y += irq2axi.c

src/soc/mediatek/mt8196/dvfs.c

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <arch/cache.h>
+#include <device/mmio.h>
+#include <soc/dvfs.h>
+
+void dvfs_init(void)
+{
+	uint32_t val;
+
+	val = BIT(8) | BIT(0);
+
+	write32p(CSRAM_BASE + 0x8, 0x55AA55AA);
+	write32p(CSRAM_BASE + 0xC, val);
+
+	dcache_clean_invalidate_by_mva((void *)CSRAM_BASE, CACHE_LINE);
+}

src/soc/mediatek/mt8196/include/soc/addressmap.h

@@ -4,6 +4,7 @@
 #define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_ADDRESSMAP_H__
 
 enum {
+	SRAM_BASE		= 0x00100000,
 	MCUSYS_BASE		= 0x0C000000,
 	MCUPM_CFG_BASE		= 0x0C240000,
 	MCUPM_SRAM_BASE		= 0x0C250000,

src/soc/mediatek/mt8196/include/soc/dvfs.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef __SOC_MEDIATEK_MT8196_DVFS_H__
+#define __SOC_MEDIATEK_MT8196_DVFS_H__
+
+#include <soc/addressmap.h>
+
+#define CACHE_LINE	64
+#define CSRAM_OFFSET	0x0001BC00
+#define CSRAM_BASE	(SRAM_BASE + CSRAM_OFFSET)
+
+void dvfs_init(void);
+
+#endif