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soc/mediatek/mt8196: Add GCE ddren sel control to mminfra

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MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction
ACK from SPM: 0, non-SPM: 0x1.

In MT8196, SPM has masked all the DDR requests, so this setting should
be set to non-SPM whenever mminfra is powering on. Otherwise, GCE will
hang when accessing DRAM.

BUG=b:379039600
TEST=boot up ok, GCE can access DRAM continuously

Change-Id: I30309b0426f803e28858eb15652a649927f94c7e
Signed-off-by: Jason-jh Lin <jason-jh.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit is contained in:
Jason-jh Lin 2025-01-13 00:26:14 +08:00 • committed by Yidi Lin
commit 0dbef76544
2 changed files with 3 additions and 0 deletions
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1
src/soc/mediatek/mt8196/include/soc/mminfra.h
View file

@ -4,6 +4,7 @@
#define __SOC_MEDIATEK_MMINFRA_H__
/* mminfra_ao */
#define MMINFRA_GCE_DDREN_SEL (MMINFRA_AO_CONFIG + 0x418)
#define MMINFRA_GCE_PROT_EN (MMINFRA_AO_CONFIG + 0x428)
/* mminfra0 */

2
src/soc/mediatek/mt8196/mminfra.c
View file

@ -26,11 +26,13 @@ static void mm_gce_lock_prot_en(void)
GCE_D_SLEEPPORT_RX_EN | GCE_D_HAND_SLEEPPORT_RX_EN |
GCE_D_HAND_SLEEPPORT_TX_EN | GCE_M_SLEEPPORT_RX_EN |
GCE_M_HAND_SLEEPPORT_RX_EN | GCE_M_HAND_SLEEPPORT_TX_EN);
write32p(MMINFRA_GCE_DDREN_SEL, 0);
}
static void mm_gce_release_prot_en(void)
{
write32p(MMINFRA_GCE_PROT_EN, 0);
write32p(MMINFRA_GCE_DDREN_SEL, 0x1);
}
static void mm_infra0_lock_prot_en(void)