Configure "cpu_ratio_override" to 0x20 (32) for the Fatcat baseboard.
This ensures the Panther Lake SoC initializes with the correct
base frequency ratio to meet the performance and thermal targets
defined for this hardware revision.
BUG=none
BRANCH=none
TEST=Build and boot Fatcat; verify CPU base frequency has updated.
Change-Id: I7ea6c7dccaf731bab1256b3297d83518ceea532c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91648
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Additionally, guard USB camera GPIO enablement using dedicated
Kconfig option.
This reverts commit bbbc655b15.
Reason for revert: FW should enable the GPIO_USB_CAM_ENABLE (206).
Change-Id: I7966240939c51a4be7027debb0a66d3e11cb75cc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Replace checked-in .spd.hex blobs with .spd.json attribute descriptions
and generate the .spd.hex at build time via spd_gen.
Change-Id: I777b12df911576c684ee8146f5ec69e61b0cc772
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91292
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace checked-in .spd.hex blobs with .spd.json attribute descriptions
and generate the .spd.hex at build time via spd_gen.
Change-Id: Ibfe5672ba9c4ffb3dcd328d9bf7df81395a3d93f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Replace checked-in mt62f2g64d8 .spd.hex blobs with .spd.json attribute
descriptions and generate the .spd.hex at build time via spd_gen.
Change-Id: I383b044f87c7ff9eaa57da580cd39a67c36c7b32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Allow mainboards to provide SPD sources as .spd.json alongside existing
.spd.hex files. When a JSON source is used, spd_gen is invoked at build
time to generate the corresponding .spd.hex in the build directory.
Change-Id: Ie1f2b81bcc15af65f1402b31f5c1f0553217fdda
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
screebo/kanix use rt1019 speaker, rt5682 headphone. karis uses rt5650
speaker and rt5650_hp headphone. All of them use 2ch-pdm0 for dmic.
This configuration is used for CoolStar's Windows audio drivers on
these devices.
TEST=build/boot Win11 on screebo, verify built-in audio functional with
coolstar's drivers.
Change-Id: Ie0be2b2d7cc41548bbe3e5b47a8e0f6039c4b2d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Use the new API to pass the microcode update pointer to the OpenSIL
so that OpenSIL can update microcode on all cores/threads during CCX
initialization.
TEST=See microcode is updated on BSP in OpenSIL on Gigabyte MZ33-AR1.
Change-Id: Ic35784583a1494ea162dc4a0d2fea8c9c3e1ef5f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Expose API to return the microcode update block address. It will be
used to provide a pointer to microcode update to the OpenSIL.
Change-Id: I1a5a89a5ff2ed29621e856cf274434803005aff8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89108
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Linux complains about these missing.
Tested with fedora 43 and CrabEFI payload.
Change-Id: I4c65760e64d8dc9b953f6a5b7f1bdcde0ce946a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91649
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FSP for Arrow Lake supports Meteor Lake, so re-point coreboot
at that, as it's, simply, newer and better.
Change-Id: I524dc7c0632c9f38b178ad95563128b56f94f983
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add two functions for disabling/enabling PCIe clocks to devices
connected to root ports. These functions are used during device power
sequencing at boot to ensure clocks are not driven to devices when
their power is off. This prevents potential issues with PCIe link
training and ensures proper power-on sequencing for connected devices.
BUG=none
TEST=Build and boot Panther Lake platform. Verify PCIe devices enumerate
correctly and clock management functions properly during power sequences
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I63f8e331b6ab18172fa32ff5c1539c71823aa247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91550
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since USB-A was removed from the mica hardware design, the Kconfig has
been configured to skip the relevant initialization.
BUG=b:488906616
TEST=emerge-bluey coreboot
Change-Id: I69cc994c83d78da87ddb95cbf471726a492512ef
Signed-off-by: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Generate RAM ID for BWMYAX32P8A-32G
DRAM Part Name ID to assign
BWMYAX32P8A-32G 4 (0100)
BUG=b:488993502
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I496292fa20884262c32d339b8448490f09c7b12b
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91508
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Add LGD touchscreen for kaladin
BUG=b:484114852
TEST=build and flash on kaladin,verify touch function works normally
Change-Id: I1f204569767e7eab17bc44dcd060d606ba87a38e
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
A local patch providing basic 2x scaling in edk2 means that the
fixed resolution VBTs are no longer needed so always use the
native-resolution VBT by default,
Remove the CFR option to pick which VBT to use, so only the native
resolution VBTs are used and included.
Change-Id: Ib7f4c546a01ebfba963b7591af9d5e24c0611206
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91618
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The panel uses TPS65130RGER as the bias IC, with supply set to ±5.9V.
Configure TPS65130RGER initialization and power-on sequence according
to the tps65130.pdf.
The tps65132s driver is no longer used on this platform and remove it
from the build.
[INFO ] mtk_display_init: 'BOE NS130069' 3504x2190@120Hz bpp 4
BUG=b:463911061
TEST=Check display initialization log and display are normal
BRANCH=none
Change-Id: Idfc19597c4357adb818ca008f93bac2e7ebe3edb
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91424
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch enables dtt and ish in devicetree for ojal and updates
FW config for GPIO's config according to schematics revision 0.9.
RDC kit no:840138
BUG=b:437459757
TEST=Build ojal board and check dmesg for errors.
Change-Id: If2ece13575ebad661cc7de78e77e3bf2f30e69e1
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aralguppe, Sowmya <sowmya.aralguppe@intel.com>
Reviewed-by: Bhat D, Krishna P <krishna.p.bhat.d@intel.com>
Add HAVE_SHARED_PS2_PORT Kconfig, associated cmos.[layout,default]
and CFR entries to p8z77-m[_pro], p8z77-v[_le_plus], p8h77-v,
where their owners manual indicate a single shared PS/2 port, to enable
control of this one port's role. Adds an "auto" option if PS/2 keyboard
init is enabled in Kconfig, to enable switching role automatically if
a device (ie. mouse) is detected on auxiliary channel.
TEST=Logitech M-S48 PS/2 mouse and various PS/2 keyboards all work with
correctly set port role and "auto" on asus/p8z77-m under a Linux
Mint 22.2 live environment.
Change-Id: I21b73da99168e751b1a23485d4b1695963f9eef5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Three more recent nvram options were not covered by checksum.
Change-Id: I69dcd3f0b57464e284965e31153e2ee0a1a80631
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This reverts commit d912ae91b0.
Reason for revert: These GPIOs will be managed by the OS.
BUG=b:481123667
Change-Id: Ieab7a9eba09c6a1128fe4709603f3b9d64e72e93
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
fwupd shows the ESRT (UEFI System Resource Table) version as 0 when
DRIVERS_EFI_MAIN_FW_VERSION is left at the default. That makes it easy
to ship firmware with no meaningful ESRT version and forces maintainers
to duplicate versioning in multiple places.
If DRIVERS_EFI_MAIN_FW_VERSION is 0, parse a leading "<major>.<minor>"
from LOCALVERSION (ignoring non-digits before/after) and encode it as
(major << 16) | minor (e.g. "v26.01-rc1" -> 0x001A0001).
If DRIVERS_EFI_MAIN_FW_LSV is 0, default it to the effective firmware
version. This provides a sane, more secure default (prevents accidental
rollback to older versions) while still allowing platforms to override
LSV explicitly when rollback is desired.
Test=boot adl/horizon and check `fwupdmgr get-devices` shows a
version:
├─System Firmware:
│ Device ID: f48f261c7fc0724729b817bfd4e8340e3195a6bc
│ Current version: 26.3
Change-Id: I3f47ee7a38e79312532f4ed5d4516c57911f727e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90861
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`register "cnvi_bt_core"` was missed in the upstream patch, so re-add
it.
Change-Id: I2be5303563f22a642c03719a16b1c88cd8d196a7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Refactor the TTB memory region definition to support stage-specific
usage. Certain boot modes require separate TTB regions for early stages
(such as bootblock or romstage) and for later ramstage usage. On Bluey,
the off-mode/low-battery charging path requires this separation because
the boot IMEM, where the early-stage TTB resides, becomes unavailable
once the ADSP comes out of reset.
This change ensures that the correct TTB region is selected for each
stage and prevents early‑stage memory constraints from impacting the
ramstage boot flow.
BUG=b:436391478
TEST=Able to build and boot google/bluey.
Change-Id: I8cedab8c744220599527de1c303a777f9ff8b1da
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Implement logic to detect and clear ChromeOS EC AC-unplug events and
provide visual feedback via the LEDs before system shutdown.
Key changes:
- Added `detect_ac_unplug_event` and `clear_ac_unplug_event` to
monitor power source changes via EC host events.
- Implemented `indicate_charging_status` to provide a 4-second
notification to the user before the AP powers off.
- Integrated these helpers into `launch_charger_applet` to ensure
the event state is clean upon entry and the user is notified
before the system issues a power-off due to charging timeouts or
state changes.
BUG=none
BRANCH=none
TEST=On Bluey, verify the LED turns on for 4 seconds when
charging fails or AC is removed during the charging applet
before the device powers off.
Change-Id: Ie1ff5ba6f158fe7302e523f984c5e5d5f05d6eae
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Refactor the low-power/off-mode charging logic into a dedicated
helper function `handle_low_power_charging_boot`.
Additionally, replace the `return` statement with `halt()` after
the charging applet logic. This ensures that if the system is in
a low-power charging state, it cannot accidentally proceed with
the rest of the mainboard initialization, which could lead to
unstable behavior or power-sequencing issues.
Included <halt.h> to provide the necessary definition.
BUG=none
BRANCH=none
TEST=Build and boot on google/quartz. Verify that low-battery boot
correctly enters the charging applet and does not proceed to full init.
Change-Id: I4bf9bb0f89d117fea9b81a5f8369fa23043a1e82
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When the charger applet times out waiting for charging to enable, the
previous behavior was to simply return. This caused a boot hang because
the system would attempt to continue mainboard initialization without
properly initialized IPs or sufficient power.
Update the timeout handler to trigger a system power-off via
google_chromeec_ap_poweroff(). This ensures the device enters a clean
G3 state if charging cannot be established, preventing a partial-boot
hang and unnecessary power drain.
BUG=none
BRANCH=none
TEST=Verified on Bluey that a charging timeout results in a clean
power-off instead of a system hang.
Change-Id: Iae00e6df39e9d78cd5d27770b871ff2e8c4c9b7c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Select EC_GOOGLE_CHROMEEC_LED_CONTROL for the following Fatcat
variants:
- Lapis
- Moonstone
- Ruby
This enables the firmware to drive system LED behavior via the
ChromeOS EC.
BUG=none
BRANCH=none
TEST=Build and boot on fatcat variants, verify LED functionality.
Change-Id: I506420c8594f5cd183cdd02c8516c053205423e3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Select EC_GOOGLE_CHROMEEC_LED_CONTROL for both BOARD_GOOGLE_MODEL_QUARTZ
and BOARD_GOOGLE_MODEL_MICA. This allows the firmware to communicate
with the EC to manage system LED states.
BUG=none
BRANCH=none
TEST=Build and boot on Bluey baseboard variants.
Change-Id: I53270c6a917c57ba8500f1fae46aac78ba43b351
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91596
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure power state thresholds (PS1, PS2, PS3) according to the
platform design specification. These thresholds define current limits
at which the voltage regulator domains transition between different
power states for optimal power management.
Ref=830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with following
VR parameter
[SPEW ] (MAILBOX) PS1Threshold = 80 (1/4 Amp)
[SPEW ] (MAILBOX) PS2Threshold = 20 (1/4 Amp)
[SPEW ] (MAILBOX) PS3Threshold = 4 (1/4 Amp)
Change-Id: I8ecb55741901eb997d78a3f1fd09175c3ce31544
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Extend fast voltage mode configuration to IA Domain
Ref=830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with following
VR parameter
[SPEW ] IccMaxItrip[0] = 152
Change-Id: Iced5cea1bed8f215602ac1455ded214fa1f72c72
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Introduce IOAPIC_USE_PRESET_ID Kconfig option to instruct coreboot to
keep the IOAPIC ID programmed in the silicon initialization modules.
For example, OpenSIL already programs the IOAPIC IDs.
TEST=See IOAPIC IDs are starting with 240 on Gigabyte MZ33-AR1 as set
by OpenSIL.
Change-Id: Idb44c1aa663d7e351b011f4dd13f0b6b426566bb
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
LZ4 decompression was being incorrectly disabled in romstage when a
separate romstage was used and CONFIG_COMPRESS_RAMSTAGE_LZ4 was not
enabled. This occurred because ENV_RAMSTAGE_LOADER is defined as
ENV_SEPARATE_ROMSTAGE in such configurations, causing
cbfs_lz4_enabled() to hit the ramstage-loader check and return false.
This regression was introduced by commit f12d2997fc ("lib/cbfs:
Don't include unused LZ4 code to shrink postcar stage"), which added
the ramstage-loader check to avoid including the LZ4 decompressor in
the postcar stage when it's not needed for the ramstage.
This patch adds an explicit check for ENV_ROMSTAGE_OR_BEFORE and
CONFIG_COMPRESS_PRERAM_STAGES to ensure LZ4 remains enabled in these
stages regardless of the ramstage compression settings.
BUG=none
TEST=Verified on Quartz
Change-Id: Icf5a2848ffe4c830bd462ab5dc7782afea3616e5
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91581
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 835b63980d, which was causing a boot failure on the ocelot DDR5 RVP. Reverting until further debugging.
BUG=b:490040385
Change-Id: I6fa397d26c57c5fb2dd415eaf8ebe5c20476b5f3
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91577
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This reverts commit 42210fdb28, which was causing the
ocelot DDR5 RVP to not boot. Reverting until further debugging.
BUG=b:490040385
Change-Id: I5185a036ccbd6cca19eb1a3fd762686ed03919e8
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91576
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The acoustic noise test fail on lapis, based on power engineer's suggestion, modify the relevant parameters in overridetree.cb.
BUG=b:482855004
TEST=emerge-fatcat coreboot, test pass by power engineer
Change-Id: I5ab48ed56fc04d57dd5c02d5512891b17147d391
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91562
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The eDP AUX controller currently sets the NO_SEND_STOP flag for all
I2C-over-AUX transactions. This prevents the controller from issuing
an I2C STOP condition, which is required for proper completion of
multi-block (extended) EDID reads.
Update edp_msg_fifo_tx() to only set the EDP_AUX_TRANS_CTRL_NO_SEND_STOP
flag when the DP_AUX_I2C_MOT (Middle-of-Transaction) bit is set in the
request. This allows the I2C transaction to correctly finalize with a
STOP condition when MOT is not present, enabling successful reads of
EDID extension blocks.
BUG=none
TEST=Verify extended EDID is correctly read on Google/Quartz.
Change-Id: I4b637a750ef16148895332abfd9ca202b5a35408
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91579
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It sets the PCH generic I/O decode range #1, meant for hardware monitor
functionalities, which are same across all variants with no reason to
deviate from. Move it into baseboard devicetree.cb.
TEST=Timeless binaries remain identical for all variants.
Change-Id: I7eecb81c02ed8c4b9bceb4cf9aff92a2bbe54ad7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91306
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the API used to configure Soundwire GPIOs to the LPASS GPIO
configure API, as these GPIOs are controlled by the LPASS subsystem.
Applies to the Soundwire amplifier GPIOs:
- GPIO_SNDW_AMP_0_ENABLE (GPIO 204)
- GPIO_SNDW_AMP_1_ENABLE (GPIO 205)
- GPIO_SNDW_0_SCL (GPIO 202)
- GPIO_SNDW_0_SDA (GPIO 203)
Test=1. Create an image.serial.bin and verify it boots successfully on
X1P42100.
2. Dump the corresponding TLMM GPIO CFG register and verify if the
eGPIO bit is disabled. The register details are part of HRD-X1P42100-S1
document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
Change-Id: I9cc16b659fc5302ef81951ffbad8e62ce90e2890
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Introduce a new API to handle configuration of LPASS GPIOs. The TLMM
GPIOs include an eGPIO enable bit that determines which subsystem
controls the GPIO. When set, the APPS processor controls the GPIO.
When cleared, the GPIO is controlled by the LPASS subsystem.
For GPIOs intended for LPASS, this API avoids enabling the eGPIO bit,
ensuring the GPIO remains controlled by the LPASS subsystem.
Test=Create an image.serial.bin and verify it boots successfully on
X1P42100.
Change-Id: Iccb51d3f5e6be4c1fadfdc7b9778805ae3e66af7
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In dt_copy_subtree(), the device_tree_node copying
*dst_node = *src_node;
doesn't work correctly for circular linked lists [1], because the 'next'
pointer of the last element isn't modified to point to the dst head.
As the only public caller of dt_copy_subtree() is dt_apply_overlay(),
and the dt_apply_overlay() function comment already explicitly disallows
'overlay' accesses after the call, fix the problem by utilizing
list_move() for copying device tree node properties and children.
Also add a new test case test_dt_apply_overlay.
[1] commit 23c41622a9 ("commonlib/list: Change to circular list")
BUG=b:434080284
TEST=emerge-rauru coreboot libpayload
BRANCH=none
Change-Id: I166ab74c9de67330d52f94e92b5d7ce5ddefa82b
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91558
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
This function transfers all elements from one list head to another. The
The destination list head takes ownership of all nodes from the source
list head. The source list head is reinitialized to an empty list.
This is useful for efficiently moving list contents without element-wise
relinking, particularly in contexts like device tree overlay application
where node structures are incorporated from a temporary tree.
BUG=b:434080284
TEST=emerge-rauru coreboot libpayload
BRANCH=none
Change-Id: I143394e381fa72bcba692b7727f57dfc09fda70e
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Rename the devtree_update() bootstate hook added in commit f8494fbeae
("lib: Add devtree_update bootstate hook") to mb_devtree_update()
for clarity, since it is a mainboard-provided hook.
Update all declarations, definitions, and call sites accordingly.
TEST=build Starlabs Starfighter MTL
Change-Id: Id7fd9811433a668905d8439b90a8ee34a472d117
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove the explicit devtree_update() call from mainboard configuration.
The devtree_update hook is provided by src/lib/devtree_update.c and runs
at BS_PRE_DEVICE. Drop the variant declarations from variants.h and add
the devtree_update header in each variant devtree.c so their overrides
are used via the common mechanism.
TEST=build/boot Starlabs Starfighter MTL
Change-Id: Ia7ceaaefe717566c6411f86d81d3a76bdfb2b2ea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91573
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
