mb/google/ocelot/var/ojal: Enable dtt and ish based on FW config
This patch enables dtt and ish in devicetree for ojal and updates FW config for GPIO's config according to schematics revision 0.9. RDC kit no:840138 BUG=b:437459757 TEST=Build ojal board and check dmesg for errors. Change-Id: If2ece13575ebad661cc7de78e77e3bf2f30e69e1 Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aralguppe, Sowmya <sowmya.aralguppe@intel.com> Reviewed-by: Bhat D, Krishna P <krishna.p.bhat.d@intel.com>
This commit is contained in:
Varun Upadhyay
Matt DeVillier
parent
df470521a7
commit
391d5f3cb4
2 changed files with 175 additions and 0 deletions
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@ -142,6 +142,36 @@ static const struct pad_config cnvi_disable_pads[] = {
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PAD_NC(GPP_F05, NONE),
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};
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static const struct pad_config ish_disable_pads[] = {
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/* GPP_B06: C_EC_ISH_ALRT */
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PAD_NC(GPP_B06, NONE),
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/* GPP_B07: SLATEMODE_HALLOUT_SNSR_R */
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PAD_NC(GPP_B07, NONE),
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/* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */
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PAD_NC(GPP_B18, NONE),
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/* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */
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PAD_NC(GPP_B19, NONE),
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/* GPP_B23: ISH_GP_6_SNSR_HDR */
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PAD_NC(GPP_B23, NONE),
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/* GPP_D06: ISH_UART0_ECAIC_TXD */
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PAD_NC(GPP_D06, NONE),
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};
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static const struct pad_config ish_enable_pads[] = {
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/* GPP_B06: C_EC_ISH_ALRT */
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PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
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/* GPP_B07: SLATEMODE_HALLOUT_SNSR_R */
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PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
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/* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
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/* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */
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PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
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/* GPP_B23: ISH_GP_6_SNSR_HDR */
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PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
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/* GPP_D06: ISH_UART0_ECAIC_TXD */
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PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
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};
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static const struct pad_config touchpad_lpss_i2c_enable_pads[] = {
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/* GPP_H20: SOC_I2C_0_SCL */
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PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
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@ -265,6 +295,12 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads);
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}
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if (fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) {
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GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads);
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} else {
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GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
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}
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if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) {
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GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads);
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} else {
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@ -38,6 +38,11 @@ end
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chip soc/intel/pantherlake
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register "power_limits_config[WCL_CORE]" = "{
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.tdp_pl1_override = 10,
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.tdp_pl2_override = 35,
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}"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port
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@ -129,6 +134,132 @@ chip soc/intel/pantherlake
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device ref iaa off end
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DDR_SOC""
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register "options.tsr[1].desc" = ""Ambient""
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register "options.tsr[2].desc" = ""Charger""
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register "options.tsr[3].desc" = ""wwan""
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## Active Policy
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# FIXME: below values are initial reference values only
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register "policies.active" = "{
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[0] = {
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.target = DPTF_TEMP_SENSOR_0,
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.thresholds = {
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TEMP_PCT(70, 97),
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TEMP_PCT(65, 90),
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TEMP_PCT(60, 80),
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TEMP_PCT(55, 75),
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TEMP_PCT(50, 65),
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TEMP_PCT(45, 45),
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TEMP_PCT(43, 30),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_1,
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.thresholds = {
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TEMP_PCT(70, 97),
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TEMP_PCT(65, 90),
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TEMP_PCT(60, 80),
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TEMP_PCT(55, 75),
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TEMP_PCT(50, 65),
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TEMP_PCT(45, 45),
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TEMP_PCT(43, 30),
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}
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},
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[2] = {
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.target = DPTF_TEMP_SENSOR_2,
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.thresholds = {
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TEMP_PCT(75, 90),
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TEMP_PCT(70, 80),
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TEMP_PCT(65, 70),
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TEMP_PCT(60, 50),
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}
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},
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[3] = {
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.target = DPTF_TEMP_SENSOR_3,
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.thresholds = {
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TEMP_PCT(75, 90),
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TEMP_PCT(70, 80),
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TEMP_PCT(65, 70),
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TEMP_PCT(60, 60),
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TEMP_PCT(55, 50),
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TEMP_PCT(50, 40),
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TEMP_PCT(45, 30),
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}
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}
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}"
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## Passive Policy
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# TODO: below values are initial reference values only
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000),
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[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
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[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000),
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}"
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## Critical Policy
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# TODO: below values are initial reference values only
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
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[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
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}"
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## Power Limits Control
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 25000,
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.max_power = 25000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 95000,
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.max_power = 95000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 3000 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 90, 6700, 220, 2200, },
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[1] = { 80, 5800, 180, 1800, },
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[2] = { 70, 5000, 145, 1450, },
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[3] = { 60, 4900, 115, 1150, },
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[4] = { 50, 3838, 90, 900, },
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[5] = { 40, 2904, 55, 550, },
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[6] = { 30, 2337, 30, 300, },
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[7] = { 20, 1608, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "true"
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register "options.fan.step_size" = "2"
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device generic 0 alias dptf_policy on end
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end
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end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp1 on end
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device ref tcss_xhci on
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@ -163,6 +294,14 @@ chip soc/intel/pantherlake
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end
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end
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device ref ish on
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probe ISH ISH_ENABLE
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chip drivers/intel/ish
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register "add_acpi_dma_property" = "true"
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device generic 0 on end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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