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vendorcode/amd/opensil/turin_poc: Pass microcode pointer to OpenSIL

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Use the new API to pass the microcode update pointer to the OpenSIL
so that OpenSIL can update microcode on all cores/threads during CCX
initialization.

TEST=See microcode is updated on BSP in OpenSIL on Gigabyte MZ33-AR1.

Change-Id: Ic35784583a1494ea162dc4a0d2fea8c9c3e1ef5f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit is contained in:
Michał Żygowski 2025-09-09 10:35:48 +02:00 • committed by Matt DeVillier
commit 88eea9da6d
1 changed files with 12 additions and 0 deletions
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12
src/vendorcode/amd/opensil/turin_poc/ramstage.c
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@ -15,6 +15,7 @@
#include <amdblocks/reset.h>
#include <bootstate.h>
#include <cbmem.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
@ -293,6 +294,8 @@ static void configure_sdxi(void)
static void configure_ccx(void)
{
CCXCLASS_DATA_BLK *ccx_data = SilFindStructure(SilId_CcxClass, 0);
UCODEPATCH_BIOSENTRYINFO *ucode_info;
void *ucode;
if (CONFIG(XAPIC_ONLY) || CONFIG(X2APIC_LATE_WORKAROUND))
ccx_data->CcxInputBlock.AmdApicMode = xApicMode;
@ -305,6 +308,15 @@ static void configure_ccx(void)
ccx_data->CcxInputBlock.EnableSvmX2AVIC = 1;
ccx_data->CcxInputBlock.EnableSvmAVIC = true;
ccx_data->CcxInputBlock.AmdCStateIoBaseAddress = ACPI_CSTATE_CONTROL;
ucode = amd_microcode_find();
if (!ucode) {
printk(BIOS_ERR, "OpenSIL: CPU microcode not found\n");
return;
}
ucode_info = &ccx_data->CcxInputBlock.UcodePatchEntryInfo;
ucode_info->UcodePatchEntryAddress = (uint64_t)ucode;
}
void setup_opensil(void)