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mb/asus/p8x7x-series/*tree.cb: Consolidate gen1_dec into baseboard

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It sets the PCH generic I/O decode range #1, meant for hardware monitor
functionalities, which are same across all variants with no reason to
deviate from. Move it into baseboard devicetree.cb.

TEST=Timeless binaries remain identical for all variants.

Change-Id: I7eecb81c02ed8c4b9bceb4cf9aff92a2bbe54ad7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91306
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui 2026-02-16 21:08:59 -05:00 • committed by Matt DeVillier
commit fd5f062446
8 changed files with 1 additions and 8 deletions
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1
src/mainboard/asus/p8x7x-series/devicetree.cb
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@ -21,6 +21,7 @@ chip northbridge/intel/sandybridge
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_switchable_ports" = "0x0000000f"
register "gen1_dec" = "0x000c0291" # Hardware Monitor
device ref xhci on end
device ref ehci2 on end

1
src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb
View file

@ -6,7 +6,6 @@ chip northbridge/intel/sandybridge
device ref peg60 on end # PCIEX16_3 (electrical x4)
subsystemid 0x1043 0x84ca inherit
chip southbridge/intel/bd82x6x
register "gen1_dec" = "0x000c0291"
register "usb_port_config" = "{
{ 1, 0, 0 },
{ 1, 0, 0 },

1
src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb
View file

@ -20,7 +20,6 @@ chip northbridge/intel/sandybridge
{ 1, 0, 5 },
{ 1, 0, 6 }
}"
register "gen1_dec" = "0x000c0291"
device ref pcie_rp1 on end # PCIEX16_2 (electrical x4)
device ref pcie_rp5 on end # AR8161 GbE NIC
device ref pcie_rp6 on end # ASM1083 PCI Bridge

1
src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
View file

@ -5,7 +5,6 @@ chip northbridge/intel/sandybridge
subsystemid 0x1043 0x84ca inherit
device ref peg11 hidden end # These don't exist on this board
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "gen1_dec" = "0x000c0291"
register "usb_port_config" = "{
{1, 8, 0}, /* Port 0: USB3 front internal header, top */
{1, 8, 0}, /* Port 1: USB3 front internal header, bottom */

1
src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
View file

@ -4,7 +4,6 @@ chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x1043 0x84ca inherit
chip southbridge/intel/bd82x6x
register "gen1_dec" = "0x000c0291"
register "gen4_dec" = "0x0000ff29"
register "pcie_port_coalesce" = "true"
register "usb_port_config" = "{

1
src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb
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@ -21,7 +21,6 @@ chip northbridge/intel/sandybridge
{ 1, 2, 5 },
{ 1, 2, 6 }
}"
register "gen1_dec" = "0x000c0291"
device ref gbe on end
device ref pcie_rp1 on end # PCIEX_16_3 (electrical x1 or x4)

1
src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/overridetree.cb
View file

@ -23,7 +23,6 @@ chip northbridge/intel/sandybridge
{ 1, 0xa53, 5 },
{ 1, 0xa53, 6 }
}"
register "gen1_dec" = "0x000c0291" # NCT6779 HWM
register "gen4_dec" = "0x0000ff29" # Could be for KB3722 EC
device ref pcie_rp1 on # PCIEX_16_3 (electrical x2 or x4)

2
src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb
View file

@ -21,8 +21,6 @@ chip northbridge/intel/sandybridge
{ 1, 0, 6 }
}"
register "gen1_dec" = "0x000c0291"
device ref pcie_rp1 on end # PCIEX16_2 (electrical x4)
device ref pcie_rp5 on end # RTL8111 GbE NIC
device ref pcie_rp6 on end # ASM1083 PCI Bridge