Some SoC like Glinda,
1. It has multiple L3 caches block, each identified by a unique cache
UID. Each core is associated with a specific L3 cache, which can be
determined based on the CPU core ID.
2. Each CPU core have slightly different CPU boost frequency.
For L3 cache info in DMI table type 7, the default implementation
(x86_get_cpu_cache_info) retrieves cache information only for the
current core and assumes that the same L3 cache is shared across all
cores.
To accurately determine the total L3 cache size:
1. Retrieves L3 cache information for each CPU core.
2. Identifies the unique cache ID associated with each core.
3. Aggregates cache sizes for all unique cache IDs to compute the
total L3 cache size, ensuring correct summation even when L3 cache
blocks have different sizes.
Additionally to get core max boost frequency,
1. Determine max boost frequency among all cores & update
smbios_cpu_get_max_speed_mhz such that it return max of all cores.
TEST=Build for Glinda SoC & check output of `dmidecode -t 7` &
`dmidecode -t 4`. Verify DMI Type7 table to report L3 cache size as 24MB
(16 + 8) & Also verify DMI Type4 'Max Speed: 5408 MHz' which is maximum
boost clock frequency.
Change-Id: I2569a9c744f7f41e4df692626e77a178184b7e0e
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
To promote code reuse and maintainability, move i2c functions to common
folder. The function prototype "mtk_i2c_bus_init(uint8_t bus)" used by
some legacy platforms are changed to "mtk_i2c_bus_init(uint8_t bus,
uint32_t speed)" for better API integration.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I6ac7009f5af4e6379d3f73aec61d0f4abd28471c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87352
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The parameter CPU isn't used, thus drop it.
Change-Id: Ie7f6179f0545f905463752e94243b438143d8234
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This patch adds Wildcat Lake-specific CPU and PCIe device IDs to the
header files and driver-specific code.
Reference:
Wildcat Lake Processor Prelim External Device IDs (820363)
BUG=b:394208231
TEST=Verified on Wildcat Lake Simulation Platform
Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87262
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I97d5d8b78cc9e5516dbfc64f81a925b1715b941b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I1c51e653a9e34bb7f5ac07bcae8481be269f83cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the
option API, so they can be configured at runtime without recompilation.
The Aperture size falls back to the FSP default value, so no change if
unconfigured.
Change-Id: Idad22ca79c10d575320b4360ec24c2019a837446
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add an option variable 'me_disable' to control the visibility of the
HECI PCI device at runtime. Default to the Kconfig selection if not set.
Change-Id: I6e7c018115780c74f1662948ed8dad3e0559051a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: Id69295ae1708164b1afbafe5724e19bf13fc3963
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87393
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the IGD config options IgdDvmt50PreAlloc and ApertureSize to the
option API, so they can be configured at runtime without recompilation.
The Aperture size falls back to the FSP default value, so no change if
unconfigured.
Change-Id: Ic900cb7bdc6dc532aef0c0b51b32bf8308a8ae36
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87392
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: I1684439755db9d8194ac5533513e65c9ba8f0768
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79917
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 2fdfa50437.
Reason for revert: libbl31.a is under refactoring. Stop linking to this
library before finalizing the binary. This patch will be re-landed when
the binary is ready.
BUG=b:412560091
Change-Id: Ie2c315141a51f30027414cfe59552cb50f2b52f6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87414
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On SoCs like Glinda, CPU cores may exhibit slight variations in
maximum boost frequency, and the L3 cache can be composed of
multiple blocks with different sizes and unique IDs.
Add helper functions,
1. get_max_boost_frequency() to compute max boost frequenncy.
2. ap_stash_core_info() to update core_info struct with max boost
frequency & all L3 cache block uniq ID & its size.
To accurately determine the total L3 cache size:
1. Retrieve L3 cache information for each CPU core.
2. Identify the unique cache ID associated with each core.
3. Aggregate cache sizes for all unique cache IDs to compute the
total L3 cache size, ensuring correct summation when L3 cache
blocks have different sizes.
TEST=Build for Glinda SoC, with L3 cache = 16MB + 8MB. Ran command
'dmidecode -t 7' & verified L3 cache is 24MB(Previously it was
wrongly reported as 32MB).
Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85640
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous implementation used _PS0 and _PS3 methods to control the
device power states. These are now replaced by a _S0W object to better
align with both coreboot's existing RTD3 driver, and the examples in
the ACPI specification.
This ensures that the Bluetooth device is recognized as capable of
reaching D3Hot when the system is in S0.
Test=build and boot starlite_adl with Windows and Linux, check Bluetooth
is functional and power draw decreases ~0.4W with no devices connected.
Change-Id: I6762b4a2a2454d4e4de2b25e3e5db17df5a8fc63
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a check in the _ON method, similar to coreboot's ONSK handling
in its RTD3 driver, to determine whether the enable GPIO is already
asserted.
This prevents the OS from repeatedly invoking _ON, which can happen
because CNVi takes around 300ms to initialize after the GPIO is
enabled.
Change-Id: I53986aa11714666c12056460aa47396266a00a1c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The definitions were reversed, as PCH_S should use 0x44, and all others
0x80.
These values can be seen in SlimBootloader, and most UEFI firmwares.
Change-Id: Ia2e3866ef7d0756220f15a8d2bdf639ac6667738
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87323
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Similarly to how things are done for the I2C controller configuration,
implement the 'soc_get_i3c_ctrlr_info' function in all SoCs that have
I3C controllers. This function returns the contents of the SoC's
'i3c_ctrlr' array containing the base addresses and ACPI names of the
I3C controllers. This function will eventually be called by the common
I3C code which will be implemented in future patches.
Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87280
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that we require the FMAP to start at offset 0 in the flash, we can
assume this across the entire codebase and therefore simplify it on
several ends.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ieb1a23f9c0ae8c0e1c91287d7eb6f7f0abbf0c2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86771
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Duty Cycle Correlation (DCC) analyzes and optimizes the relationship
between the duty cycles of multiple signals. This commit implements DCC
driver support to improve clock signals, power management, and
communication systems, enhancing system stability and performance.
These improvements will become more significant as the SoC ages.
BUG=b:389784352
BRANCH=rauru
TEST=Build pass, check dcc log:
[DEBUG] [DCC] DSU=0x0, LCPU=0x0, MCPU=0x17, BCPU=0x1b
Change-Id: I77e5cd951f45dad7a6e2e77c135b821e4179e019
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87320
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Make mt6359p_read_field() a general API usable by multiple drivers,
instead of a static function limited to the original driver.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I2d9c3de9ad08f918a84fa63c1e9b3af7adc5974a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87336
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Since infracfg.h is not used in pmif_spi.c, remove its inclusion to
prevent build errors in projects that don't have infracfg.h.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I09229ff370a53407b3f0c290704887de367ed80b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87339
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch overrides the FSP-M UART MMIO base address to ensure the FSP
GFX PEIM can output debug console messages when required.
Currently, the default UART MMIO base used by FSP-M/S might not be the
intended console UART for debug output in boot stages, particularly for
the GFX PEIM. By overriding it with the value derived from
`CONFIG_UART_FOR_CONSOLE` when either `PcdSerialDebugLevel` or
`SerialDebugMrcLevel` is non-zero, we ensure that debug logs are
directed to the configured console.
This change is crucial for debugging issues within the GFX PEIM
initialization process.
BUG=b:380375181
TEST=Verified that enabling FSP debug tokens after this change allows
viewing debug output from the GFX PEIM during display initialization.
Steps to reproduce:
1. Flash an AP FW image (`image.fatcat.serial.bin`).
2. Observe the absence of debug output from the GFX PEIM during display
initialization.
3. Dynamically enable the FSP debug token using
```
sudo cbfstool image-fatcat.serial.bin add-int -i 3 -n option/fsp_pcd_debug_level
```
4. Flash the modified AP FW image.
5. Observe debug output from the GFX PEIM during display initialization
```
[INFO]:[IsGraphicsDeviceSupported()]...
[INFO]:[GetVbtStartAddress()]
```
Change-Id: I835ef75cb3046217127823c92f708bfe4f3ff741
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87318
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add the Amston Lake (9W) with MCH_ID 0x4674 to the vr_config table.
Based on Intel docs 721616 rev 2.3.
BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor
Change-Id: I7249d3223ccbb1671a0b84da1c2347737e1aec89
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87246
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
A 'quirks' variable is added for panels that require special handling
in the display driver due to sensitivity to the eDP signal quality. The
display driver can then handle the special requests accordingly.
On Navi, the swing level needs to be increased to 3 (500mV) for the
ATNA40HQ01-0 panel to resolve a flickering issue.
BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
[INFO ] fw_config match found: OLED_WQXGA_PLUS=PRESENT
...
[INFO ] update_swing_preemphasis: Force swing setting to 3 (500 mV)
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: Ifa8c45050f61d3dff1fa7aed8fa8e435391a6f3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Select RESET_VECTOR_IN_RAM from the common SOC_AMD_COMMON_BLOCK_NONCAR
Kconfig option instead of selecting it in each AMD SoC's Kconfig which
selects SOC_AMD_COMMON_BLOCK_NONCAR.
From family 17h on, the AMD SoCs don't use cache as RAM (CAR) any more.
In most cases, including the coreboot case, the PSP puts coreboot's
bootblock into DRAM, thus RESET_VECTOR_IN_RAM needs to be selected.
There might be a case where the RESET_VECTOR_IN_RAM part isn't true, but
that isn't specific to a SoC generation, so even this unlikely case
doesn't prevent us from moving the selection of the Kconfig option to
the common non-CAR Kconfig option.
Change-Id: I87d7908f94505647f504f9d214e3c52f9c3a3715
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87322
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for DPTC by calling SB.DPTC() as part of PNOT().
Change-Id: I29d7177c96217bf03eaea818cfc1f944f4e640a6
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87218
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It doesn't cause any problems, because the next line is empty. But it
is wrong nonetheless.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I8f1e99e06575e769f5698e4cd86e44f0b4df8a07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87289
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `spi_ctrlr_bus_map` defines the range of SPI bus numbers managed
by different controllers. Previously, the generic `spi_qup_ctrlr`
was hardcoded to manage buses 0 through 15.
Modify the `.bus_end` value for the `spi_qup_ctrlr` entry to be
`QUPV3_SE_MAX - 1`.
TEST=Able to build google/herobrine.
Change-Id: I7e9ec555a6d72d93bc23285e48eab52030978e1a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
APU_I2C*_BASE are defined in the SoC's iomap.h, so include it.
Change-Id: Id7b1674914a045699d6df53b20e35028c3936f67
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87281
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the description of PMC GPIO_CONF register from
EHL EDS Vol 2 Book 2 rev 2.3 #614109.
Some of the groups had incorrect values or even defined
non-existent GPIO groups.
TEST=Boot Protectli VP2420 to Ubuntu 24.04.
Change-Id: I910f3c4c0d31b8d24b83cd2c3a28688b898b5d9f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87050
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This reverts commit 4b5a490b6f.
Reason for revert: This effort was apparently given up on since 4 years.
So remove the function, since it is not used at the moment. If someone
wants to bring that effort back to live, said person can feel free to do
so.
Change-Id: I26d5c9fbfd6eae24f876d857a6e952ca0d1a64ae
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add Raptor Lake P specific PCIe root port ID.
Based on intel document 640552 rev 2.81.
BUG=NA
TEST=Customer platform with Raptorlake-P
Change-Id: Ifa7c131b5ae47294c055b9e68dad2764607c032b
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87244
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Intel processor number X7433RE.
Based on docs 721616 rev 2.3.
BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor
Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Add the AOAC IDs of the I3C controllers. The following documentation was
used to verify this:
Genoa: #55901 Rev 0.40
Mendocino: #57243 Rev 3.08
Rembrandt: #56558 Rev 3.09 (in Mendocino directory)
Phoenix: #57019 Rev 3.09
Glinda: #57254 Rev 3.00
Faegan: #57928 Rev 1.51 (in Glinda directory)
Change-Id: I54d049c58756251506f94d220e1970ccec170918
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87279
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add minimal common AMD I3C controller code that reports the MMIO region
used by the different I3C controllers to the resource allocator. For
this to work, select the introduced SOC_AMD_COMMON_BLOCK_I3C Kconfig
option and add the 'soc_amd_i3c_mmio_ops' device operations to the I3C
device devicetree entries on all SoCs that include I3C controllers.
Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add the base addresses of the I3C controllers and the mmio devices to
the devicetree for the SoCs that have I3C controllers. The following
documentation was used to verify this:
Mendocino: #57243 Rev 3.08
Rembrandt: #56558 Rev 3.09 (in Mendocino directory)
Phoenix: #57019 Rev 3.09
Glinda: #57254 Rev 3.00
Faegan: #57928 Rev 1.51 (in Glinda directory)
For Genoa, those entries already existed in both its iomap.h and its
devicetree. Cezanne and Picasso don't have I3C controllers.
Change-Id: I6e8073e6498266b909b6cc5f589353f2ed23a62f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87276
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST: Tested by entering ACPI S3 sleep state and pressing any key
on USB keyboard wakes up the system.
Change-Id: Ieed635a7199f53c2e7c69c8f17b3ef50b76b8d91
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87287
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make sure that the ROM2 MMIO area starts at flash address 0.
Document 56780
Change-Id: I1fc06517ea496441147375579800f7349e39facc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
When a SPI ROM greater than 16MByte is being used it will be split
into 16MByte chunks that can be remapped in HW as an automatic recovery
mechanism. As an example when the EFS in the first 16MByte is corrupted
and the second 16MByte EFS is valid the HW will switch pages. The automatic
address translation of the MMIO ROM needs to be accounted when accessing
the ROM2/ROM3 BAR.
Add a function to retrieve the current address remapping and print it in
show_spi_speeds_and_modes() for debugging purposes.
Document 56780
Change-Id: I046e029e6135ab57f79b675c62b233203f00d705
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87175
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The explicit selection of `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` for
Panther Lake SoC has been removed.
Panther Lake platforms inherently enable display across all boot
modes (normal, developer, recovery) when vboot is active.
Therefore, explicitly selecting `VBOOT_MUST_REQUEST_DISPLAY`
becomes redundant, especially when `VBOOT_ALWAYS_ENABLE_DISPLAY`
is enabled due to the selection of `BMP_LOGO` for ChromeOS
devices.
TEST=Able to perform ec sync without any additional reboots.
Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87284
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
