soc/mediatek/mt8196: Add DCC driver support in ramstage

Duty Cycle Correlation (DCC) analyzes and optimizes the relationship
between the duty cycles of multiple signals. This commit implements DCC
driver support to improve clock signals, power management, and
communication systems, enhancing system stability and performance.
These improvements will become more significant as the SoC ages.

BUG=b:389784352
BRANCH=rauru
TEST=Build pass, check dcc log:
[DEBUG]  [DCC] DSU=0x0, LCPU=0x0, MCPU=0x17, BCPU=0x1b

Change-Id: I77e5cd951f45dad7a6e2e77c135b821e4179e019
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87320
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/mt8196/Makefile.mk

@@ -55,6 +55,7 @@ romstage-y += thermal.c
 romstage-y += thermal_sram.c
 
 ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
+ramstage-y += dcc.c
 ramstage-y += ddp.c
 ramstage-y += ../common/display.c
 ramstage-y += ../common/dpm_v2.c

src/soc/mediatek/mt8196/dcc.c

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <soc/dcc.h>
+
+void dcc_init(void)
+{
+	/* DSU */
+	clrbits32p(BUS_PLLDIV_CFG1, GENMASK(20, 16));
+	/* LCPU */
+	clrbits32p(CPU_PLLDIV_0_CFG1, GENMASK(20, 16));
+	/* MCPU */
+	clrsetbits32p(CPU_PLLDIV_1_CFG1, GENMASK(20, 16), BIT(20) | GENMASK(18, 16));
+	/* BCPU */
+	clrsetbits32p(CPU_PLLDIV_2_CFG1, GENMASK(20, 16), GENMASK(17, 16) | GENMASK(20, 19));
+
+	printk(BIOS_DEBUG, "[DCC] DSU=%#x, LCPU=%#x, MCPU=%#x, BCPU=%#x\n",
+	       (read32p(BUS_PLLDIV_CFG1) >> 16) & 0x1F,
+	       (read32p(CPU_PLLDIV_0_CFG1) >> 16) & 0x1F,
+	       (read32p(CPU_PLLDIV_1_CFG1) >> 16) & 0x1F,
+	       (read32p(CPU_PLLDIV_2_CFG1) >> 16) & 0x1F);
+}

src/soc/mediatek/mt8196/include/soc/dcc.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_MT8196_DCC_H
+#define SOC_MEDIATEK_MT8196_DCC_H
+
+#include <soc/addressmap.h>
+
+#define BUS_PLLDIV_CFG1		(MCUSYS_BASE + 0x0104) /* DSU */
+#define CPU_PLLDIV_0_CFG1	(MCUSYS_BASE + 0x0110) /* LCPU */
+#define CPU_PLLDIV_1_CFG1	(MCUSYS_BASE + 0x011C) /* MCPU */
+#define CPU_PLLDIV_2_CFG1	(MCUSYS_BASE + 0x0128) /* BCPU */
+
+void dcc_init(void);
+
+#endif /* SOC_MEDIATEK_MT8196_DCC_H */

src/soc/mediatek/mt8196/soc.c

@@ -3,6 +3,7 @@
 #include <bootmem.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <soc/dcc.h>
 #include <soc/dramc_info.h>
 #include <soc/emi.h>
 #include <soc/gpueb.h>
@@ -52,6 +53,7 @@ static void soc_init(struct device *dev)
 {
 	uint32_t storage_type = mainboard_get_storage_type();
 
+	dcc_init();
 	mtk_fsp_init(RAMSTAGE_SOC_INIT);
 	mtk_fsp_add_param(FSP_PARAM_TYPE_STORAGE, sizeof(storage_type), &storage_type);
 	add_pi_image_params();