soc/amd: add functions to retrieve I3C controller info

Similarly to how things are done for the I2C controller configuration,
implement the 'soc_get_i3c_ctrlr_info' function in all SoCs that have
I3C controllers. This function returns the contents of the SoC's
'i3c_ctrlr' array containing the base addresses and ACPI names of the
I3C controllers. This function will eventually be called by the common
I3C code which will be implemented in future patches.

Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87280
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/common/block/include/amdblocks/i2c.h

@@ -68,6 +68,11 @@ struct i2c_pad_control {
 	enum i2c_pad_rx_level rx_level;
 };
 
+struct soc_i3c_ctrlr_info {
+	uintptr_t bar;
+	const char *acpi_name;
+};
+
 void fch_i2c_pad_init(unsigned int bus,
 		      enum i2c_speed speed,
 		      const struct i2c_pad_control *ctrl);
@@ -94,4 +99,7 @@ void i2c_soc_init(void);
 /* Reset I2C peripherals. */
 void sb_reset_i2c_peripherals(const struct soc_i2c_peripheral_reset_info *reset_info);
 
+/* Getter function to get the SoC I3C controller information. */
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs);
+
 #endif /* AMD_COMMON_BLOCK_I2C_H */

src/soc/amd/genoa_poc/Makefile.mk

@@ -5,6 +5,7 @@ all-y		+= reset.c
 all-y		+= config.c
 all-y		+= gpio.c
 all-y		+= i2c.c
+all-y		+= i3c.c
 all-y		+= uart.c
 
 bootblock-y	+= early_fch.c

src/soc/amd/genoa_poc/i3c.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/i2c.h>
+#include <soc/iomap.h>
+#include <types.h>
+
+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}

src/soc/amd/genoa_poc/include/soc/iomap.h

@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		6
 #define I2C_PERIPHERAL_DEV_COUNT	0
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4
 
 #define SPI_BASE_ADDRESS		0xfec10000
 

src/soc/amd/glinda/Makefile.mk

@@ -14,6 +14,7 @@ all-y		+= i2c.c
 
 # all_x86-y adds the compilation unit to all stages that run on the x86 cores
 all_x86-y	+= gpio.c
+all_x86-y	+= i3c.c
 all_x86-y	+= uart.c
 
 bootblock-y	+= early_fch.c

src/soc/amd/glinda/i3c.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/i2c.h>
+#include <soc/iomap.h>
+#include <types.h>
+
+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}

src/soc/amd/glinda/include/soc/iomap.h

@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		4
 #define I2C_PERIPHERAL_DEV_COUNT	0 /* TODO: Only master for now. */
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4
 
 #if ENV_X86
 

src/soc/amd/mendocino/Makefile.mk

@@ -11,6 +11,7 @@ all-y		+= i2c.c
 
 # all_x86-y adds the compilation unit to all stages that run on the x86 cores
 all_x86-y	+= gpio.c
+all_x86-y	+= i3c.c
 all_x86-y	+= uart.c
 
 bootblock-y	+= early_fch.c

src/soc/amd/mendocino/i3c.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/i2c.h>
+#include <soc/iomap.h>
+#include <types.h>
+
+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}

src/soc/amd/mendocino/include/soc/iomap.h

@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		4
 #define I2C_PERIPHERAL_DEV_COUNT	0 /* TODO: Only master for now. */
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4
 
 #if ENV_X86
 

src/soc/amd/phoenix/Makefile.mk

@@ -14,6 +14,7 @@ all-y		+= i2c.c
 
 # all_x86-y adds the compilation unit to all stages that run on the x86 cores
 all_x86-y	+= gpio.c
+all_x86-y	+= i3c.c
 all_x86-y	+= uart.c
 
 bootblock-y	+= early_fch.c

src/soc/amd/phoenix/i3c.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/i2c.h>
+#include <soc/iomap.h>
+#include <types.h>
+
+static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
+	{ APU_I3C0_BASE, "I3C0" },
+	{ APU_I3C1_BASE, "I3C1" },
+	{ APU_I3C2_BASE, "I3C2" },
+	{ APU_I3C3_BASE, "I3C3" }
+};
+
+const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
+{
+	*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
+	return i3c_ctrlr;
+}

src/soc/amd/phoenix/include/soc/iomap.h

@@ -6,6 +6,7 @@
 #define I2C_MASTER_DEV_COUNT		4
 #define I2C_PERIPHERAL_DEV_COUNT	0 /* TODO: Only master for now. */
 #define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
+#define I3C_CTRLR_COUNT			4
 
 #if ENV_X86