If the system is powered on while the lid is closed (e.g., via a
power button or auto-power-on event), there is no need to initialize
the internal display.
Update display_startup() to check the lid state via get_lid_switch().
Skipping initialization in this state reduces unnecessary power
consumption and slightly improves boot time for closed-lid scenarios.
BUG=none
TEST=Verify display does not initialize when lid is closed on
Google/Quartz.
Change-Id: I2ec48876f102b7309a1401aa9d7bdc0fdc96791a
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91011
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the ChromeEC driver now supporting lid state retrieval via host
commands for non-LPC platforms, enable VBOOT_LID_SWITCH for Bluey.
This allows the mainboard to utilize vboot features that depend on
the lid status, such as preventing boot when the lid is closed.
BUG=none
TEST=Verify LID status on Google/Quartz.
Change-Id: Idfc45258170e86a673aede9fc63a87a9a2ca3c3b
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91009
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On non-LPC platforms (such as those using I2C or SPI for EC comms),
the EC memory map is not directly accessible via memory-mapped I/O.
Instead, these platforms must use the EC_CMD_READ_MEMMAP host command
to retrieve system information.
Implement google_chromeec_get_switches() using this host command for
non-LPC systems. This enables get_lid_switch() to function correctly
on eSPI-based and other non-LPC mainboards, allowing them to support
lid-controlled logic.
BUG=none
TEST=Verify the LID state using get_lid_switch() on Google/Quartz.
Change-Id: Ic7dbe1bcf6b528dfefc168e2f0de0357430dc84d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Correct the GPP_V17 gpio pin from platform reset to deep to
avoid uncontrollable behavior in s0ix mode.
BUG=b:475990377
BRANCH=none
TEST=Build and boot to OS, check GPP_V17 behavior is correct.
Change-Id: I8f8bc59b71b8f8b4c5d4dbdbdcf8fcbfdbd96921
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91050
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
BUG=b:452180266
BRANCH=none
TEST=Build and check system can boot to OS
Change-Id: I6092f620f4ae0635ffbbd9c26cf0ce0d55b44ba8
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91048
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Increase the maximum root port count for Panther Lake (PTL) to 12.
While the actual number of active ports may vary depending on the
specific SKU and strapping, setting this constant to 12 is safe
and systematically handled by the existing SoC logic.
Systematic Bounds: The common PCIe root port driver (pcie_rp.c)
and PTL-specific FSP parameter logic utilize ptl_rp_groups and
PCI configuration space accesses to determine the actual hardware
limits at runtime.
Safe Ceiling: CONFIG_MAX_ROOT_PORTS serves as a compile-time upper
bound for array allocations and iteration loops. Setting this to
12 accommodates the maximum possible PTL configuration without
over-allocating resources.
Consistency: This aligns the configuration with the hardware's
maximum capability, allowing the silicon initialization code to
dynamically "fill in" the details for lower-port SKUs without
requiring further Kconfig changes.
BUG=None
TEST=Able to build boards that use different PTL SKUs.
Change-Id: Icb8f2c075aa56531e311d1ce718953fe3366a5e2
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91078
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 261274992d.
Reason for revert: Panther Lake U/H Processor EDS vol 1/2 says PTL-U/H
12Xe has 12 PCIe RPs where else PTL-H 4Xe has 10 PCIe RPs.
This change has limit the capability for devices that is build with
PTL-U/H 12Xe hence, we are seeing below errors
```
[ERROR] pcie_rp_update_devicetree: Error: Group exceeds
CONFIG_MAX_ROOT_PORTS.
```
As a result PCIe Gen 5 devices (SSD) unable to init and enabled during
boot.
Change-Id: I0443554ef8f619c485f16edc576794f9cf2e85ea
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91075
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit dec1dfe160.
Reason for revert: It is causing ADSP load failure in the OS.
BUG=b:480195888
TEST=Able to load the ADSP on Google/Quenbi.
Change-Id: I029c2b7ba74764a15227e44edc3be755cb8b9363
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91072
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
configure_tdp() selects the power limit table based on the
SA PCI device ID and the CPU's nominal TDP.
Add a 45W entry for PCI_DID_INTEL_ARL_H_ID_1 (e.g. Intel
285H) so power limits are programmed instead of being
skipped.
Change-Id: Ia90633b43b78bc616ff0b750ed3ef44333019957
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91056
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 4a09db75d9 ("util/autoport: Add
support for 9 Series PCHs (Lynx Point Refresh)") got submitted after
commit 01d82febb2 ("util/autoport:
Separate handling of Kconfig selects").
The latter commit was specifically made so that the former commit could
properly express a Kconfig select with a condition. However, the former
commit did not get updated, and got submitted as-is since there was no
unresolved review comment to keep track of this TODO. As a result, what
should have been a conditional Kconfig select but with the condition in
a comment to work around limitations of the original system accidentally
became a bool option override.
So, simply use the new system to express a conditional Kconfig select.
This fixes the wrongly-generated Kconfig as well as the original issue.
Even though this would still have worked, the `USE_BROADWELL_MRC` option
must be selected for boards with a Lynx Point Refresh PCH, since Haswell
MRC will not work on those PCHs. Still, this can be caught and corrected
during review, in case any board ports are made before this fix lands.
Change-Id: I98f032283e9e5bb5ec13dbff382304b7abfec07e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91027
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Bump the submodule and thus include the following new commits:
hw-gfx-gma-i2c: Reduce EDID I2C timeout
transcoder: Don't try to disable disabled DDI func
gfxtest: Handle 64-bit aperture base and register location
gma: Get DPCD 1.1+ displays out of D3
gma: Work around GNATprove issue with nested loops
TEST=libgfxinit still works on Lenovo X220 and is 450msec faster.
Change-Id: If32fd0256280ee8539c6bbc0440c30d89711996c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91030
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently not all fixed MMIO ranges are advertised to the resource
allocator. This is not an issue as long bottom-up allocation is
used and as long as only small PCI BARs are present on the system.
Tell the PCI resource allocator about active MCH BARs to not overlap
PCI BARs with MCH BARs.
TEST=Can still boot on Lenovo X220. No issues seen in coreboot or Linux.
Change-Id: I9148ce492b3b16542bae2737c98b0e6fd0701745
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Handle ADL-P and ADL-M PCI IDs the same as ADL-N and RPL-P for
dumping LPC registers. Add southbridge names/labels for ADL-P
and ADL-M.
TEST=build and run 'inteltool -l' to dump LPC/eSPI registers on
google/taeko (RPL-P), verify output matches LPC decode set in devicetree
Change-Id: I84901a8e25eb679acb31be1caa8fffa667454c62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In a follow-up patch (CB:90962), the list will be changed to a circular
one, and list_node fields 'next' and 'prev' will become private to the
implementation.
To allow smooth transition to circular lists for all call sites, add the
following functions to the list API:
- list_is_empty()
- list_next()
- list_prev()
- list_first()
- list_last()
- list_length()
All list API call sites are expected to use the public API instead of
the raw 'next' and 'prev' pointers.
Change-Id: Ib1040f5caab8550ea52db9b55a074d7d79c591e5
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The code was copied from newer generation SoC supporting parallel
SMM relocation, but it wasn't properly cleaned.
Gen1 doesn't support parallel SMM relocation, so fix the comments.
Change-Id: Idbe6d2c18f668a9c1922b93ce1b2cc3d126ff2f9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91013
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As discussed under CB:88768, building for PantherLake targets fails due
to odd race-condition:
```
src/include/stdint.h:66:9: error: "INT32_MAX" redefined [-Werror]
66 | #define INT32_MAX ((int32_t)0x7FFFFFFF)
| ^~~~~~~~~
[...]
129 | #define INT32_MAX (0x7FFFFFFF)
| ^~~~~~~~~
cc1: all warnings being treated as errors
make: *** Waiting for unfinished jobs....
```
Board maintainers shouldn't need to include the FSP API header in their
ports, adding this header globally to meminit.h resolves the
race-condition and allows the build to finish.
Change-Id: Id7656d476ca6db78ea74629ef37a20323362997a
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91023
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Commit dd817408e1 ("device/pci_device: Fix leftover devices") changed
the conditions for a device to be considered leftover to include not
being disabled, so update the comment to reflect that.
Change-Id: If80a5aae00ba97c1e0580dedb460a605a71bb627
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Make PCIe ASPM/L1SS CFR options depend on PCIe Clock Power Management
so the setup UI can hide them when CLK PM is disabled.
Change-Id: I7dc778bc2d6fb15d6062a4ab855bc8b700c22fad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The touchscreen device is dependent on the accelerometer on starlite_adl,
so offer the touchscreen CFR option only when the accelerometer option is
enabled.
Implement a new weak cfr_touchscreen_update() callback in the starlabs
common CFR code and override it in starlite_adl to suppress the
touchscreen option when accelerometer is disabled
Change-Id: I4bab6ccb92c40190014ab55200ff214064d5d2ae
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Update platform_romstage_pre_mem() to only trigger the red LED alert
when the lid is closed.
Previously, the critical low battery alert would trigger regardless of
the lid state. Checking the lid switch ensures the visual alert is
targeted at "closed-lid" scenarios where the user needs a physical
indicator of a power-critical state that prevents booting.
Change-Id: I9833fb26df9c31989abec142536e1fe7efb93c10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested on a HP ProDesk 400 G7, with an i5-10500 and a Q470 chipset.
Dumping MCH, SPI/BIOS CONTROL, LPC/eSPI, GPIO, EPBAR and DMIBAR work.
Change-Id: I0eca3a72c42b0cb85bcda8502bccbb4a80704b3b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The GPIO pad community definition for Skylake does not set the
pad_cfg_lock_offset member, leading to an "offset not defined for pad"
error when trying to lock a pad config in gpio_non_smm_lock_pad(). This
must be set to the offset of the first Pad Configuration Lock register
within each GPIO communities register blocks which can be found in the
GPIO sections of the processor I/O and PCH-H datasheets.
References:
Skylake-U/Y: Intel 332691
Sunrise Point-H: Intel 332996
Kaby Lake-U/Y: Intel 334659
Union Point-H: Intel 335193
Change-Id: I2991a7cbfb333d9fdda008cbb4cbc272aa508ef0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
According to EDS #872188, PTL-H484 has 8 more PCIe
lanes than PTL-H404 and 12Xe SKUs.
I believe there's been a mixup during bringup, as PCIe ACPI tables are
"gated" for an SKU with more PCIe 5.0 lanes.
To be exact, in a file: "src/soc/intel/pantherlake/acpi/ptl_pcie.asl"
we can notice PCIe 5.0 RootPorts depending on SOC_INTEL_PANTHERLAKE_H.
Google/Fatcat boards seem to be using PANTHERLAKE_U_H instead.
TEST: Build/boot intel/pantherlake_crb. Make sure Linux doesn't report
PCIe routing errors.
Change-Id: I1d136cf1959a3851d0ac37b256fd4df28a8d30df
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Generate an 'EMMC' ACPI device under the PCIe root port to which the
GL9763E is attached. The EMMC device contains a child CARD device whose
_RMV method returns 0. This allows Windows to identify the eMMC as a
fixed internal drive instead of a removable one.
This fixes an issue where the Windows 11 installer fails around 55%
with a generic 'Windows 11 installation has failed' error. Install
logs show the failure is due to Windows identifying the storage
device as removable and aborting (error 0xC1420134).
TEST=build/boot Win11 installer on google/taeko with eMMC installed,
verify Windows installer identifies it as a non-removable drive via
diskpart, and install completes successfully.
Change-Id: I51e59cb9e9dc2459724138b4bd404fb1eea64680
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Revised the GPP_E18 configuration to use GPI IRQ.
BUG=b:473955137
TEST=Confirmed that the ELAN touchpad functionality
is operating correctly,and no occurrences of the
following error message are observed in the logs:
elan_i2c i2c-ELAN0000:00: invalid report id data (0)
Change-Id: Ie8fd2f13f5db4f830e4ffcd88a5a7b55f4d9bee3
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90908
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current clang version cannot be built using GCC-15 so switch to a
more recent release.
It also adds a new dependency called third party. Its used in various
LLVM components and is needed to build clang.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0f2ebc214726fd4ae4f7bba50a662dd5cb89a718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89377
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set PcieRpSlotImplemented to 0 on the PCIe root ports which have eMMC
attached via a GL9763E bridge/controller for chronicler and elemi
variants. This ensures that FSP correctly treats these RPs as built-in
rather than slot devices.
TEST=tested with rest of patch train
Change-Id: I0e06df689164f95ee9f0253fde3df2891239fa63
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Set the PCIE_RP_BUILT_IN flag on the PCIe root ports which have eMMC
attached via a GL9763E bridge/controller for all variants using PCIe-
attached eMMC. This ensures the FSP PcieRpSlotImplemented UPD is set
properly and that FSP correctly treats these RPs as built-in rather
than slot devices.
TEST=tested with rest of patch train
Change-Id: Ifb4b255ea5367733405a7ac5d73c616ce7f8aad5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The existing Lynx Point code is known to work with 9 series PCHs, as
evidenced by commit f5105313cf ("mb/asrock/z97_extreme6: Add new
mainboard") and commit 58c7a84097 ("mb/asrock: Add Z97E-ITX/ac
(Haswell/Broadwell)"). Add the missing IDs to autoport's existing Lynx
Point code.
These IDs were taken from the Intel 9 Series Chipset Family Platform
Controller Hub datasheet (document 330550), section 1.4 "Device and
Revision ID Table".
TEST=Autoport output for the ASRock Z87E-ITX remains unchanged
TEST=Autoport generates output for the ASRock Z97E-ITX/ac
Change-Id: I94c0b35245624d1a68ab69332fe9a5c5abfc5310
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90054
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When a critical battery level is detected without a charger present,
the system must shutdown to protect the battery from deep discharge.
Previously, this was an immediate power-off with minimal feedback.
This patch improves the shutdown sequence by:
1. Adding trigger_critical_battery_shutdown() to encapsulate the
safety logic.
2. Providing visual feedback by setting the ChromeOS LED to Red
during early boot flow (at romstage) for user feedback..
3. Logging an ELOG_TYPE_LOW_BATTERY_INDICATOR event to the event log
for post-mortem analysis.
4. Introducing a 5-second delay before power-off to ensure UART
logs are flushed and the user can observe the LED alert.
The shutdown logic remains in ramstage to ensure the user is able to
see the low-battery notification before powering off the system.
TEST=Boot Bluey with battery < critical threshold and no charger:
- Observed LED turning Red.
- Observed "Critical battery level..." warning in serial log.
- System powered off after 5 seconds.
- Verified 'cbmem -l' showed the low battery event after next boot.
Change-Id: I52948eac87417bca895000cb10dbaa87bb6a9384
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90850
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, display_startup() is called near the end of mainboard_init.
If the system enters a low-power boot mode (such as low-battery or
off-mode charging), the function returns early, leaving the display
uninitialized.
Move display_startup() before the is_low_power_boot() check. This
ensures the display is ready to show user notifications, such as
battery status or charging icons, even when the rest of the
mainboard initialization is skipped.
TEST=Build and boot Google/Quartz.
Change-Id: Ibaa2b20d3ea1ca8548ea6ebf93efbc48cb7a6b95
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90968
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, the system does not explicitly distinguish between a low
battery boot with a charger and one without. This is critical for
deciding whether to allow the boot to proceed or to protect the
battery.
This patch:
1. Re-introduces LB_BOOT_MODE_LOW_BATTERY to represent a critical
battery state without a charger present.
2. Refactors set_boot_mode() to accommodate off-mode charging and
evaluating battery health (low-batter w/ or w/o charger present)..
TEST=Verified on Bluey:
- Boot with charger + low battery enters LOW_BATTERY_CHARGING.
- Boot without charger + low battery enters LOW_BATTERY..
- Boot with normal battery enters NORMAL mode.
Change-Id: I2c9fa7eb61d1bbd6f9379c81577aee53ab6a0761
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90849
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current LB_BOOT_MODE_LOW_BATTERY actually implies a state where the
battery is below the critical threshold but a charger is attached,
allowing the system to boot into a charging-only or limited state.
Update the enum name to LB_BOOT_MODE_LOW_BATTERY_CHARGING across
coreboot tables and libpayload to better reflect this hardware state.
Changes:
- Rename boot mode enums in commonlib and libpayload.
- Update bluey mainboard logic to use the more descriptive name.
- Refactor is_low_power_boot() to is_low_power_boot_with_charger()
to improve code readability.
- Ensure the charger-present condition is explicitly checked in
romstage when setting the boot mode.
TEST=Verify bluey boots into off-mode charging and low-battery
charging modes correctly.
Change-Id: I2478c7519c781a8b5af78445899b7f9bf412cf42
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This patch moves the ChromeEC battery-low LED signaling from the
Panther Lake SoC romstage code to the Fatcat mainboard-specific
romstage.
By utilizing the platform_romstage_pre_mem() hook, we remove Google-
specific EC logic from the generic Intel SoC directory, adhering better
to the separation of concerns between SoC and Mainboard code.
- Implement platform_romstage_pre_mem() in google/fatcat.
- Remove redundant EC include and LED logic from Panther Lake SoC.
Change-Id: I09f7dd516f1a98cf99313db379cfbef5157c9869
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91000
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Introduce platform_romstage_pre_mem() and platform_romstage_post_mem()
as weak symbols in the x86 romstage cycle.
These hooks allow SoCs and mainboards to execute low-level setup or
instrumentation immediately before and after memory initialization
without modifying the core romstage.c flow.
- platform_romstage_pre_mem: Called before mainboard_romstage_entry.
- platform_romstage_post_mem: Called after memory is up but while still
running on the Cache-as-RAM (CAR) stack.
Change-Id: I59cb115de0d512106d9a029d683c10b025076893
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90999
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement google_chromeec_is_critically_low_on_battery() to check if
the system is at risk of an imminent power-off.
This function returns true only if the battery is below the critical
threshold and no charger is detected. Combining these checks into a
single helper ensures that firmware notifications (like a red
lightbar) or emergency power-down logic do not trigger while the
device is successfully connected to AC power.
- Implement google_chromeec_is_critically_low_on_battery in ec.c.
- Export the function in ec.h for use in romstage/ramstage.
TEST=Verified on Fatcat & Bluey that the function correctly identifies
the low-power state and suppresses warnings when a charger is plugged
in.
Change-Id: I9f0f268d6660d913f989a9deffa24ab1f585b508
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90963
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Display flickering and occasional corruption were observed during panel
initialization on some TM_TL121BVMS07_00C panels when using an EMI-type
FPC.
According to Ilitek, this is caused by insufficient RX margin under
higher EMI conditions. Increasing receiver EQ, mask, bias, and voltage
settings improves signal tolerance and stabilizes display output.
Update the panel initialization code with the following parameters:
EQ:
P6_8F = 0xF0
Mask:
P8_82 = 0x13
P8_7D = 0x84
P8_7F = 0xDA
Bias:
P6_90 = 0x55
Voltage:
P5_3F = 0x47
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
BUG=b:479436242
TEST=build and check firmware screen.
BRANCH=skywalker
Change-Id: Id8272103abfb94f4d4f4d915107eafb9d0f4edc9
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Define `BOOTMEDIA_SMM_BWP`, `BOOTMEDIA_SMM_PWP_RUNTIME_OPTION` and
`DRIVERS_EFI_FW_INFO` Kconfig type as bool to satisfy Kconfig lint
requirements.
TEST=None
Change-Id: Ie798378665e6bd3e00ce271e17b36e81df92e2ad
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
protection
Add support for runtime control of BIOS lock
(BOOTMEDIA_SMM_BWP) via the CFR option API. This allows
users to enable/disable BIOS write protection in SMM
through the setup menu when explicitly enabled.
The implementation adds a new "bios_lock" CFR option that:
- Controls SMM BIOS write protection at runtime
- Sets EISS (Enable InSMM.STS) when enabled
- Enables SPI/LPC write protection in SMM
- Prevents unauthorised BIOS modifications outside SMM
Security model:
- Runtime control is opt-in via
BOOTMEDIA_SMM_BWP_RUNTIME_OPTION config
- When disabled, the option is suppressed in CFR
(not exposed in UI)
- Compile-time CONFIG(BOOTMEDIA_SMM_BWP) serves as the
default/fallback
- Protects against unauthorised EFI variable
modifications, bypassing BIOS lock when the runtime
option is not enabled
The option is integrated into Intel's common lockdown
code and SMI handlers, replacing compile-time-only
checks with conditional runtime lookups where
BOOTMEDIA_SMM_BWP_RUNTIME_OPTION is enabled.
Change-Id: Ie3b63462501e0d204c33dc3f8a006b73da0899d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89919
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the ModPHY settings are also available on other Intel platforms,
these parameters should be moved to common code.
Change-Id: Ic2666c7bbd576681dea7f360c396c068b42306e2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90943
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using this, the compiler is going to check if the printf formatting is
correct for our printk messages.
Since we already have the macro, might as well use it.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I247f24ed64c2be7fc411f5e2fdd38715698bc4e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90829
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 55a972236e ("chromeec: Disable battery remaining capacity
workaround") disabled the workaround for all ChromeEC devices, since
newer EC firmware applies compensation via battery_compensate_params.
Older boards use EC branches that lack this logic; without it, users can
see 93–100% charge–discharge cycling and stale full-capacity reporting.
Add a Kconfig to configure the workaround, and select it for older
boards whose EC firmware lacks battery_compensate_params logic.
EC firmware branches were inspected to determine which ones lack this
logic.
TEST=build/boot google/lulu, verify battery full indication works
correctly with the Kconfig selected.
Change-Id: I096e0cf402e07f846b961319e01fb8f2c2dde7fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90960
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In the first boot after coreboot is flashed, ABL FW performs
memory training and passes APOB data to coreboot. coreboot
writes APOB data in SPI flash along with hash of the APOB data.
If APOB signature is not written in CMOS, Memory context is
not restored by ABL in subsequent boot and full training is
initiated which increases boot time.coreboot keeps writing the
APOB data to flash in every boot due to hash mismatch of APOB
data which inturn increases boot time.This change fixes the
issue of ABL FW not doing Memory Context restore due to missing
CMOS signature.On some older platforms FSP writes this signature
unconditionally and hence this coreboot patch doesnt impact
the older platforms.
TEST= Validated on crater platform. APOB write is not initiated
by coreboot on every boot. APOB write to flash happens only once
after the coreboot flash.
Change-Id: Id799d0d2ed9f54e29db7681509f3d66c1638b6ac
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90947
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes logo_valignment from overridetree.cb. The alignment
`FW_SPLASH_VALIGNMENT_CENTER` is the default behavior in the coreboot
splash driver, making this explicit assignment unnecessary.
BUG=none
TEST=Build and boot lapis; verify logo remains centered.
Change-Id: Ibf3ea2a9843b31f39fd08621f6056e63c2676ff7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90965
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Fix regression introduced by commit d18cc50e6a ("soc/intel/xeon_sp:
Use common smm_relocate").
The MSR SMM_FEATURE_CONTROL_MSR is only implemented on client SoCs.
Starting from Haswell server onwards the "SMM feature control" on
server platforms resides on the UBOX in PCI space.
Parallel SMM relocation was never supported on server platforms, thus
disable parallel SMM relocation for now and thus fix booting on all
Xeon-SP platforms. Added a FIXME to possibly implement this feature
in the future.
TEST=Can boot on OCP/tiogapass again.
Change-Id: I7b4fbe633046acbf9f921cca722ff343a64962cd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
