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mb/google/brya: Mark PCIe root ports with attached eMMC as built-in

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Set the PCIE_RP_BUILT_IN flag on the PCIe root ports which have eMMC
attached via a GL9763E bridge/controller for all variants using PCIe-
attached eMMC. This ensures the FSP PcieRpSlotImplemented UPD is set
properly and that FSP correctly treats these RPs as built-in rather
than slot devices.

TEST=tested with rest of patch train

Change-Id: Ifb4b255ea5367733405a7ac5d73c616ce7f8aad5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This commit is contained in:
Matt DeVillier 2026-01-28 18:09:19 -06:00
commit fa2e54907b
12 changed files with 12 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/google/brya/variants/anahera/overridetree.cb
View file

@ -202,7 +202,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(7)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN,
}"
end #PCIE7 EMMC
device ref tcss_dma0 on

2
src/mainboard/google/brya/variants/anahera4es/overridetree.cb
View file

@ -184,7 +184,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(7)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN,
}"
end #PCIE7 EMMC
device ref tcss_dma0 on

2
src/mainboard/google/brya/variants/aurash/overridetree.cb
View file

@ -193,7 +193,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(12)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
}"
probe STORAGE STORAGE_EMMC
probe STORAGE STORAGE_UNKNOWN

2
src/mainboard/google/brya/variants/crota/overridetree.cb
View file

@ -203,7 +203,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(3)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
}"
end #PCIE3 BH799BB
device ref pcie_rp9 off end

2
src/mainboard/google/brya/variants/gladios/overridetree.cb
View file

@ -213,7 +213,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(12)]" = "{
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN,
}"
probe STORAGE STORAGE_EMMC
end #PCIE12 EMMC

2
src/mainboard/google/brya/variants/kinox/overridetree.cb
View file

@ -261,7 +261,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"

2
src/mainboard/google/brya/variants/lisbon/overridetree.cb
View file

@ -213,7 +213,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(12)]" = "{
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER | PCIE_RP_BUILT_IN,
}"
probe STORAGE STORAGE_EMMC
end #PCIE12 EMMC

2
src/mainboard/google/brya/variants/moli/overridetree.cb
View file

@ -201,7 +201,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(12)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
}"
probe STORAGE STORAGE_EMMC
probe STORAGE STORAGE_UNKNOWN

2
src/mainboard/google/brya/variants/primus/overridetree.cb
View file

@ -183,7 +183,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(3)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
}"
end #PCIE3 BH799BB
device ref tcss_dma0 on

2
src/mainboard/google/brya/variants/taeko/overridetree.cb
View file

@ -565,7 +565,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
.pcie_rp_aspm = ASPM_L1,
}"
probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED

2
src/mainboard/google/brya/variants/taniks/overridetree.cb
View file

@ -383,7 +383,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
}"
probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
end

2
src/mainboard/google/brya/variants/volmar/overridetree.cb
View file

@ -331,7 +331,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(3)]" = "{
.clk_src = 4,
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN,
}"
probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
end #PCIE3 BH799BB