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util/inteltool: Support more Comet Lake-S IDs (Q470)

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Tested on a HP ProDesk 400 G7, with an i5-10500 and a Q470 chipset.

Dumping MCH, SPI/BIOS CONTROL, LPC/eSPI, GPIO, EPBAR and DMIBAR work.

Change-Id: I0eca3a72c42b0cb85bcda8502bccbb4a80704b3b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Riku Viitanen 2025-11-12 23:05:17 +02:00 • committed by Matt DeVillier
commit 05c7869dd5
10 changed files with 44 additions and 0 deletions
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1
util/inteltool/gpio.c
View file

@ -1119,6 +1119,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
case PCI_DEVICE_ID_INTEL_HM770:
case PCI_DEVICE_ID_INTEL_WM790:
case PCI_DEVICE_ID_INTEL_HM470:
case PCI_DEVICE_ID_INTEL_Q470:
case PCI_DEVICE_ID_INTEL_C262:
case PCI_DEVICE_ID_INTEL_C266:
case PCI_DEVICE_ID_INTEL_ADL_P:

1
util/inteltool/gpio_groups.c
View file

@ -187,6 +187,7 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s
case PCI_DEVICE_ID_INTEL_HM370:
case PCI_DEVICE_ID_INTEL_CM246:
case PCI_DEVICE_ID_INTEL_HM470:
case PCI_DEVICE_ID_INTEL_Q470:
*community_count = ARRAY_SIZE(cannonlake_pch_h_communities);
*pad_stepping = 16;
return cannonlake_pch_h_communities;

11
util/inteltool/inteltool.c
View file

@ -156,6 +156,16 @@ static const struct {
"10th generation (Comet Lake-H family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2,
"10th generation (Comet Lake-H family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_S_10,
"10th generation (Comet Lake-S family) Core Processor (Desktop)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_S_8,
"10th generation (Comet Lake-S family) Core Processor (Desktop)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_S_6,
"10th generation (Comet Lake-S family) Core Processor (Desktop)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_S_4,
"10th generation (Comet Lake-S family) Core Processor (Desktop)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_S_2,
"10th generation (Comet Lake-S family) Core Processor (Desktop)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HEWITTLAKE,
"Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP,
@ -441,6 +451,7 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK_LPC, "Gemini Lake" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H570, "H570" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q470, "Q470" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM470, "HM470" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z590, "Z590" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q570, "Q570" },

6
util/inteltool/inteltool.h
View file

@ -224,6 +224,7 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_WM590 0x4389
#define PCI_DEVICE_ID_INTEL_QM580 0x438a
#define PCI_DEVICE_ID_INTEL_HM570 0x438b
#define PCI_DEVICE_ID_INTEL_Q470 0x0687
#define PCI_DEVICE_ID_INTEL_HM470 0x068d
#define PCI_DEVICE_ID_INTEL_C252 0x438c
#define PCI_DEVICE_ID_INTEL_C256 0x438d
@ -403,6 +404,11 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2 0x9b44 /* Cometlake H 8+2 (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2 0x9b54 /* Cometlake H 6+2 (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2 0x9b64 /* Cometlake H 4+2 (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_S_10 0x9b33 /* Cometlake S 10 (Desktop) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_S_8 0x9b43 /* Cometlake S 8 (Desktop) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_S_6 0x9b53 /* Cometlake S 6 (Desktop) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_S_4 0x9b63 /* Cometlake S 4 (Desktop) */
#define PCI_DEVICE_ID_INTEL_CORE_CML_S_2 0x9b73 /* Cometlake S 2 (Desktop) */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2 0x9a04 /* Tigerlake UP3 2 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4 0x9a14 /* Tigerlake UP3 4 Cores */
#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2 0x9a02 /* Tigerlake UP4 2 Cores */

1
util/inteltool/lpc.c
View file

@ -151,6 +151,7 @@ int print_lpc(struct pci_dev *sb, struct pci_access *pacc)
}
break;
case PCI_DEVICE_ID_INTEL_HM470:
case PCI_DEVICE_ID_INTEL_Q470:
dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0);
if (!dev) {
printf("LPC/eSPI interface not found.\n");

5
util/inteltool/memory.c
View file

@ -232,6 +232,11 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_10:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_8:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_6:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_4:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_2:
mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */

15
util/inteltool/pcie.c
View file

@ -327,6 +327,11 @@ int print_epbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_10:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_8:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_6:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_4:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_2:
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
break;
@ -474,6 +479,11 @@ int print_dmibar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_10:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_8:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_6:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_4:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_2:
dmi_registers = cometlake_dmi_registers;
size = ARRAY_SIZE(cometlake_dmi_registers);
dmibar_phys = pci_read_long(nb, 0x68);
@ -608,6 +618,11 @@ int print_pciexbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_10:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_8:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_6:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_4:
case PCI_DEVICE_ID_INTEL_CORE_CML_S_2:
pciexbar_reg = pci_read_long(nb, 0x60);
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
break;

1
util/inteltool/pcr.c
View file

@ -142,6 +142,7 @@ void pcr_init(struct pci_dev *const sb)
case PCI_DEVICE_ID_INTEL_C256:
case PCI_DEVICE_ID_INTEL_W580:
case PCI_DEVICE_ID_INTEL_HM470:
case PCI_DEVICE_ID_INTEL_Q470:
case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE:

1
util/inteltool/rootcmplx.c
View file

@ -126,6 +126,7 @@ int print_rcba(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_ICH5:
case PCI_DEVICE_ID_INTEL_ADL_N:
case PCI_DEVICE_ID_INTEL_HM470:
case PCI_DEVICE_ID_INTEL_Q470:
printf("This southbridge does not have RCBA.\n");
return 1;
default:

2
util/inteltool/spi.c
View file

@ -351,6 +351,7 @@ static int print_bioscntl(struct pci_dev *sb)
break;
case PCI_DEVICE_ID_INTEL_ADL_N:
case PCI_DEVICE_ID_INTEL_HM470:
case PCI_DEVICE_ID_INTEL_Q470:
bios_cntl = pci_read_byte(sb, 0xdc);
bios_cntl_register = adl_pch_bios_cntl_registers;
size = ARRAY_SIZE(adl_pch_bios_cntl_registers);
@ -534,6 +535,7 @@ static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) {
size = ARRAY_SIZE(elkhart_spi_bar_registers);
break;
case PCI_DEVICE_ID_INTEL_HM470:
case PCI_DEVICE_ID_INTEL_Q470:
if (get_espibar_phys(sb, pacc, 5, 0x10, 0xfffff000, &rcba_phys))
return 1;
rcba_size = 4096;