This board came virtually rebranded from a specific German OEM called
Wortmann AG and was identified as "TERRA_PC/H81M-D2W" model: 1009381.
It however ships a GIGABYTE GA-H81M-D2W rev 1.0 branded motherboard
which is extremely similar to a Retail GIGABYTE GA-H81M-D2V rev 1.0.
The only obvious differences are the onboard video outputs, its serial
connectivity and total abscence of it on the GIGABYTE support website.
- GA-H81M-D2W
DVI-D + DVI-I + serial port header on motherboard
- GA-H81M-D2V
DVI-D + VGA + DB9 serial port connector on backplate
Mainboard: GIGABYTE GA-H81M-D2W rev 1.0
Pure autoport (initial commit) doesn't boot, second patch brings up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, PCIe fixes enabling onboard LAN and other PCIe slots
and some IT8625E superio code from a other coreboot port made most
ITE8620E superio related functions work, especially WDT otherwise this
board resets every couple of seconds! Autoport did log hda codec / pins
but it didn't include them in the hda_verb.c, so I added them manually
which also fixes pcspkr (beep codes, not soundcard connected).
Flash instructions:
Internal flashing using flashrom works on OEM and when running coreboot
using the following command: flashrom -p internal -c "MX25L6473F" -w ROM
An external flasher ch341a_spi (3.3v mod) used with a SOIC 8 pomona
probe to recover the MX25L6473F in situ also works without issues. Only
the power of the USB programmer was used, and the board's main PSU was
disconnected during external flash!
Tested:
- coreboot 25.06-77-g812d0e2f626d as base
- EDK2 (MrChromebox/2502)
- SeaBIOS 1.16.3
- Broadwell mrc.bin (tidus)
- Haswell mrc.bin (peppy used for all mrc.bin noted testing)
- Haswell NRI
- libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
- DVI-D & DVI-I (VGA) all work during POST, BOOT and OS
- Pentium G3220 / Xeon E3-1225 v3 / Xeon E3-1231 v3
- RAM single and dual slot 2GB/4GB/8GB mixed DDR3 DIMMS max 6, 8, 16GB
(NRI & mrc.bin)
0/2: 2GB DDR3-1333 - Kingston 99U5458-001.A00LF (2010-W29)
0&2: 4GB DDR3-1600 - Kingston 9905402-174.A00G (2015-W33)
0/2: 2GB DDR3-1600 - Micron 8JTF25664AZ-1G6M1 (2013-W37)
0/2: 4GB DDR3-1600 - Samsung M378B5173BH0-CK0 (2013-W30)
(NRI single DIMM won't mix with others)
0/2: 8GB DDR3-1600 - SK Hynix HMT41GU6MFR8C-PB (2023-W20)
(ECC UDIMM, mrc.bin only, see NRI note below)
0&2: 4GB DDR3-1600 ECC - Kingston 9965432-051.A00LF (2013-W19)
0&2: 8GB DDR3-1866 ECC - Micron 18JSF1G72AZ-1G9E1 (2013-W29)
- Fedora MATE 42 (Kernel 6.14)
- KDE NEON 6.4 (Kernel 6.11)
- MS Windows 10 / 11
- Audio Outputs both DVI > HDMI, Headphone, Line Out (left&right chan.)
- Audio Input Line In (back)
- pcspkr
- USB2/3 all Intel ports
- SATA 4 ports
- PCIe slots (16x 5GT/s & both 1x 5GT/s)
- iGPU (plus dGPU as in dual GPU work both with mrc.bin / Haswell NRI)
- dGPU (nVidia GeForce GT640-2GD3 2.5GT/s / Radeon HD7770-1GB 5GT/s)
- Realtek RTL8111F onboard Gb LAN
- Wake on LAN
- HWM shows both fan speeds and voltages
- PS/2 port (both Keyboard and Mouse with Y splitter cable)
- Serial port header (coreboot console & OS)
- PowerButton (Poweron/Poweroff/Wake)
- ResetButton
- LEDs HDD & POWER (off during suspend)
- Shutdown/Reboot/Suspend
- Strip down the Intel ME/TXE firmware (make menuconfig) see ME note!
- Disabling ME HECI (manually remove from devicetree.cb) see ME note!
- flashrom -p internal -c "MX25L6473F" #read & write
Not tested:
- Audio Inputs Front & Back Microphone Ports
- parallel port header
- USBDEBUG
- VBIOS
Not working:
- Disable Intel ME PCI interface (make menuconfig)
- USB2/3 all VIA VL805 backpanel ports
FD layout note:
The original OEM firmware ships a BIOS region that seem to use the
whole firmware:
00000000:00000fff fd
00000000:007fffff bios
00001000:001fffff me
Although coreboot works fine with this flash descriptor layout it is
mandatory to flash a complete image! Replacing only a specific region
like the BIOS region when relying on --ifd will confuse flashrom and
trash the flash chip's contents! As a temporary measure one can use
--layout to flash a specific region using the following layout:
00000000:00000fff fd
00001000:001fffff me
00200000:007fffff bios
Permanently changing the flash descriptor layout to look like this will
solve flashing specific regions and remains a valid option since it
cannot break GIGABYTE its DualBIOS feature since its absent.
NRI note:
EDK2 shows 0GB instead of the actual RAM amount installed. While using
Haswell mrc.bin EDK2 shows the correct amount of RAM. The earlier noted
RAM modules have also been tested using NRI in Memtest86+ v7.20 which
still correctly displays and test the total amount of RAM.
ECC UDIMMs currently do not work on this board because NRI does
not check whether the board / chipset support ECC. This results
in RCVET failures for the ECC bytelane (byte 8). Eventually this
will be fixed in NRI. Haswell mrc.bin works as expected.
ME note:
Neutering the ME will let the system still function correctly, unless
you include EFFS and FCRS partitions addressed by ME_CLEANER_ARGS:
"-S --whitelist EFFS,FCRS"
Failing to supply these ME partitions will cripple superio functions as
in serial output (breaks coreboot serial console) and HWM fan and
voltage info goes random nuts while the fan stays at normal speed.
VIA VL805 note:
Without firmware loading (which is still unknown) and enabling it in the
devicetree.cb will give DMAR IOMMU errors therefore disabled by default!
The data.vbt blob was extracted using debugfs from the OEM F5 firmware
which enables both video outputs DVI-D and DVI-I (VGA).
Since this board is not listed on the GIGABYTE website, but it works
with the Retail GA-H81M-D2V F6 firmware I listed that one instead in the
board_info.txt. However I cannot confirm that this coreboot port also
works for the GA-H81M-D2V, it is good practice to at least check its
gpio values matching this port!
Change-Id: I80dc414a92d115099ec8966841af0cf22d5b1d09
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88412
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates GPP_F17 (CODEC_INIT_N) configuration to fix an issue
with the 3.5mm headphone jack on the I2S codec AIC not detecting
headphone plug/unplug events. Specifically, we need to configure GPP_F17 to have interrupt capability, edge detection to detect plug and unplug events, and power state persistence.
BUG=b:434208278
TEST=After booting to OS, plug and unplug a headphone to the I2S codec
add-in card, headphone is getting detected.
Change-Id: I1c662ec680d8175be5854c753ea1481d09afb561
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88564
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Becasue of requirement for VCCANA power from MBVR mode to FIVR mode,
so change ICCmax at VCCIN_AUX will be from 25A to 27A due to
internal VR.
BUG=b:417662158
TEST=Build and boot to OS at the rework motherboard and verfied by
power team.
Change-Id: Ie036412c0e435cfce39940de6bab363f9e875f42
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88558
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the machine shows circle icon instead of G icon in 'Setting'
->'Device'->'View keyboard shortcuts'.
So add MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD to enable G icon.
BUG=b:429495479
BRANCH=none
TEST= Build and boot to OS and enter 'Setting'->'Device'
->'View keyboard shortcuts' to see G icon.
Change-Id: I0a195c65fe2835f9be66c56fb7129851b3251b90
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88446
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
For the latest trulo projects: kaladin,pujjolo,pujjocent,
the original comment was too brief and led to some misunderstanding.
In the past years, only retimer has the SBU muxing function. Or said,
only retimer has Aux Orientation feature. So, 'no retimer' implies
Aux Orientation feature inside the processor is needed.
And now, the modern future PDC also has the Aux Orientation feature.
Not all "no retimer" cases require setting the override bit anymore.
The even numbered bits should be set only when there is no retimer and
the processor's Aux Orientation is still required.
(If set, the SoC inverts the orientation value coming from EC/PDC when
operating in flipped orientation.)
In the referenced issue tracker, the system has 'no retimer' and uses
a 'future PDC'. (The PDC has the Aux Orientation feature.)
Test results (DP + TCSS):
- 'tcss_aux_ori' = 0 + PDC sends orientation detected value -> PASS
- 'tcss_aux_ori' = 5 + PDC sends 'original' value -> PASS
- 'tcss_aux_ori' = 5 + PDC sends orientation detected value -> FAIL
(Fail means only display one side.)
This patch updates the comment to more accurately describe the expected
usage and avoid future confusion.
Refer doc#:
646929 TWL PDG
734752 TCSS Cookbook (MTL Backward/MTL/PTL/WCL)
627270 TWL Bios Spec
758766 MTL Bios Spec
766031 MTL PDG
BUG=b:4292672
BRANCH=none
TEST=Update coreboot device tree with different tcss_aux_ori value and
test the DP connection via TCSS on 2 orientations.
Change-Id: I3281110e522c53a35abf30fd1c372bb5ca18c10d
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88482
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP-T will help to cache bios region along with MTRR programming
by setting CodeRegionBase/CodeRegionLength, thus there is no need
for xeon_sp platforms to do it.
TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/archercity CRB
Check MTRR usage and below duplicated MTRR item get removed:
[DEBUG] 0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP
[DEBUG] 0x000fffffff000800: PHYMASK1: Length = 0x0000000001000000, Valid
Change-Id: Ia414a35c663f3aa1b02d944475a96e11d07a4f00
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Add support to increase the CPU clock frequency to 1.36(GHz).
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Create an image.serial.bin and ensure it boots on X1P42100 and
CPU runs in 1.36GHz Frequency.
Change-Id: Ie51e032141bdfabf4c96b6891ec9f084561d97ff
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement the two functions defined as prototypes in gpio.h.
Allows to drop custom SMI handler code and use the generic function
from gpio.c instead.
Change-Id: I795af83374118d3fc2b46837b1822205c966fda6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88508
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of open coding what gpio_base2_value() does use the
function to get the GPIO states of the ID pins.
Change-Id: Ib09993998f7e8ee2a7e5295f49ed14058a095eb0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88505
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I8c83b3436818275958cd8eb8b1c0d7b235e0344c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88504
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to retrieve the value of multiple GPIOs
at once as integer value and use the generic function prototype
defined in include/gpio.h instead.
Therefore:
* select GENERIC_GPIO_LIB
* Stub gpio_input(). Existing code assumes the pin is input.
* Drop get_gpios() implementation
* Include new header file gpio.h
* Migrate pins from type int to gpio_t
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I2296ff72231b569c618295b36b95a89ffebb3a6e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88503
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I714eaf2115a455d327e6b2313dafd0e293bee8a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In order to use the common gpio.h header file typedef gpio_t in
soc/gpio.h for Intel common code, Intel lynxpoint and Intel broadwell.
Change-Id: I2049a2cfd75c60d00bdd564b294808760b6aff7f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Include the missing header stdbool.h
Fixes compilation error
hybrid_graphics.h:6:28: error: unknown type name 'bool'
while refactoring some code.
Change-Id: I96f7255049cd9e24d74838a173e920a00636b09e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88546
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When moving headers compilation can fail as pmh7.h is missing
the include for type bool. Add the missing include to make sure
future code refactoring works.
Fixed the error:
src/ec/lenovo/pmh7/pmh7.h:27:1: error: unknown type name 'bool'
Change-Id: Ib0a2489a0c461bf021168e98737ecb6062caa696
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename config options 'USE_DDRx' to 'DRAM_SUPPORT_DDRx' to make them
less clunky, and in preparation to expand their use inside SoC code.
Change-Id: Ie6edd730c5cbad679a90fcf7989a942d9b2dd3d8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <yuchi.chen@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update hda_verb table for pujjocento to optimize noise floor.
BUG=b:433647377
TEST=emerge-nissa sys-boot/coreboot sys-boot/chromeos-bootimage
Verify that the noise floor on AP is less than -90 dB when
DUT plays mute.wav.
Change-Id: Ib8642a88bb707e99c3d459eb70a6fdf5562f4c75
Signed-off-by: lizheng <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88549
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kaladin need to set this config since we use unified firmware for UFS and non UFS skus
BUG=b:432579255
TEST=Flash and boot on every sku on kaladin
Change-Id: I5fa8f51776e6ba13e9003ea7913c2b4784b76217
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88475
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add DRAM part H58G56CK8BX146
BUG=b:432397864
TEST=Flash and boot to OS successfully on kaladin
Change-Id: Id880940d608c76b88e384ee2cbea03eec8e35b53
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88469
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves the shrm_fw_load_reset() API from the SC7280 specific
implementation to the Qualcomm common directory. This change enables
reuse of the API across multiple Qualcomm chipsets.
Change-Id: Ifab870b9aea7396e29fa93c999c29cf11ab0d199
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88545
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set `TPM_TIS_ACPI_INTERRUPT` to 49 (GPE0_DW1_17) for all ocelot
variants using `BOARD_GOOGLE_MODEL_OCELOT` instead of
`BOARD_GOOGLE_OCELOT`.
BUG=b:433177132
TEST=Able to boot Ocelot
Change-Id: I662e1b38530861da008cf54da4a31dd0ac6212c8
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Disable CNVi bluetooth in the baseboard by default. This will be
enabled per variant basis based on the WIFI fw_config in variant.c
file.
BUG=b:433215861
TEST=Able to connect to boot Ocelot and connect to bluetooth.
Below error is not seen when WIFI_PCI_6/7 selected.
```
[ERROR] CNVi BT is enabled without CNVi being enabled
```
Change-Id: Ibe5d22c013852f868a2a3296c79dfdf1de7c1455
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88551
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit introduces changes to support the FATCAT4ES board variant
by updating the EC command range configuration. The changes updates the
gen1_dec register to configure correctly to accomdate the FATCAT4ES
variant which ensures the ec-host communication should not fail. Also it
ensures other conditional checks in the EC header file for enabling this
new variant.
BUG=b:432676108
TEST=Build with the FATCAT4ES configuration and verify ec host
communication is not failing.
Change-Id: I5c84dc2161847f9fe4316c0e63aa876696947423
Signed-off-by: Megha Verma <megha.verma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88552
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes redundant touchscreen GPIO configurations from
romstage_gpio_table. These GPIOs are no longer required to be explicitly
set for the touchscreen while using ACPI for touchscreen power
sequencing.
When the generic.use_gpio_for_status flag is enabled, the touchscreen
driver's power resource method will perform a probe to determine the
device's operational status. This probe specifically verifies two
critical conditions:
- The Enable GPIO pin is enabled (HIGH).
- The Reset GPIO pin is not in reset (LOW).
If both of these conditions are met, the touchscreen is considered ready
and functional.
Conversely, if either of these conditions is not met, the _ON method
within the power resource will be invoked. The _ON method is then
responsible for executing the full touchscreen initialization sequence
to bring the device into an operational state.
BUG=b:430444353
TEST=Able to build and boot google/kinmen. Verified touchscreen is
working as expected with this patch.
Change-Id: I0bb2e1ddd4168ef1831b30817dbb3bc3f6e6a5d2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit transitions the touchscreen power sequencing for the Karis
variant from static coreboot GPIO configuration to ACPI-driven
management. This allows the kernel's touch driver to handle the power
sequencing, providing more flexible and dynamic control.
Redundant touchscreen GPIO configurations are removed from
early_gpio_table, and romstage_gpio_table. These GPIOs are no
longer required to be explicitly set in coreboot given the shift to ACPI
power sequencing.
The generic.use_gpio_for_status register is set to true in the
device's override tree to enable ACPI power sequencing for touchscreen
signaling.
When the generic.use_gpio_for_status flag is enabled, the touchscreen
driver's power resource method will perform a probe to determine the
device's operational status. This probe specifically verifies two
critical conditions:
- The Enable GPIO pin is enabled (HIGH).
- The Reset GPIO pin is not in reset (LOW).
If both of these conditions are met, the touchscreen is considered ready
and functional.
Conversely, if either of these conditions is not met, the _ON method
within the power resource will be invoked. The _ON method is then
responsible for executing the full touchscreen initialization sequence
to bring the device into an operational state.
BUG=b:430444353
TEST=Able to build and boot google/kanix. Verified touchscreen is
working as expected with this patch.
Change-Id: I5c049c76fed185a40c31a6e779119c953926e6c9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit transitions the touchscreen power sequencing for the Karis
variant from static coreboot GPIO configuration to ACPI-driven
management. This allows the kernel's touch driver to handle the power
sequencing, providing more flexible and dynamic control.
Redundant touchscreen GPIO configurations in bootblock and romstage are
removed from early_gpio_table, and romstage_gpio_table. These GPIOs are
no longer required to be explicitly set in coreboot given the shift to
ACPI power sequencing.
The generic.use_gpio_for_status register is set to true in the
device's override tree to enable ACPI power sequencing for touchscreen
signaling.
When the generic.use_gpio_for_status flag is enabled, the touchscreen
driver's power resource method will perform a probe to determine the
device's operational status. This probe specifically verifies two
critical conditions:
- The Enable GPIO pin is enabled (HIGH).
- The Reset GPIO pin is not in reset (LOW).
If both of these conditions are met, the touchscreen is considered ready
and functional.
Conversely, if either of these conditions is not met, the _ON method
within the power resource will be invoked. The _ON method is then
responsible for executing the full touchscreen initialization sequence
to bring the device into an operational state.
BUG=b:430444353
TEST=Able to build and boot google/karis. Verified touchscreen is
working as expected with this patch.
Change-Id: I967650290dda9ca3ca66a2f161fff0ae84b14f04
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88516
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8189 uses MT6359 clk_buf, and will use new RC mode with srclken_rc.
The clk_buf will provide several 26M clocks, and these clocks can be
independently turned on.
BUG=b:379008996,b:422503190,b:403478729
BRANCH=none
TEST=show driver init log:
RG_CENTRAL_CFG1: 0x104014e5
RG_CENTRAL_CFG2: 0x1010
RG_CENTRAL_CFG3: 0x400f
Signed-off-by: LiLiang Chen <liliang.chen@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ia04526d55191c695caf3ef40002e1ec99f299966
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88525
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces support for asynchronous coreboot File
System (CBFS) file loading from SPINOR, specifically targeting the
fsps.bin file, in the Intel Panther Lake (PTL) System on a Chip (SoC)
platform. The primary motivation for this change is to improve boot time
performance by utilizing SPI Direct Memory Access (DMA) to preload files
while the Central Processing Unit (CPU) continues executing other tasks.
This feature uses cooperative multithreading. Because the scheduling is
cooperative, the boot process stays mostly predictable, which minimizes
debugging difficulties while still enhancing boot performance.
The preload operations are strategically modified according to the
chipset lockdown settings. This guarantees that payload preloading is
finalized prior to SPI DMA locking when the chipset lockdown is managed
by FSP or otherwise maximizes the pre-loading feature.
Note: As there is no UPD to control the Fast DMI DMA interface lockdown,
a special FSP binary, built without the Fast SPI DMA driver
(PcdSpiDmaEnable), is required when chipset lockdown setting is set to
CHIPSET_LOCKDOWN_COREBOOT.
TEST=On a Fatcat device, with CHIPSET_LOCKDOWN_COREBOOT, the boot time
has improved by around 17-18 ms.
Change-Id: I4106058d382b99eac5f988c134cc02f024f7d473
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88300
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit implements a token-based queuing system to reduce delays
between consecutive DMA operations. The queuing mechanism aims to
improve overall throughput.
A Kconfig option FAST_SPI_DMA_QUEUE_SIZE defines the maximum number of
concurrent DMA transfers that can be queued and processed.
When DMA transfers are queued, a new thread is initiated to run
fast_spi_dma_main_thread(). This function consistently monitors for
available transfer tokens and performs DMA operations when tokens are in
the DMA_REQUESTED state. If there are no tokens in the desired state,
the thread_running flag is set to false, and the thread terminates
smoothly.
While it provides a barely perceptible boot time improvement with the
Panther Lake configuration, it makes the boot flow more consistent and
predictable.
TEST=On a Fatcat device with CBFS_PRELOAD enabled and set up, we observe
consecutive logs as follows, proving a new DMA transfer is issued
as soon as the previous one's completion is detected.
[DEBUG] Fast-SPI: transfer completed in 2574 us
[DEBUG] Fast-SPI: Reading 240 blocks via DMA
Change-Id: Ic5249362041cfa028885874b43893e1d7942ed94
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
In PTL Crashlog Watcher interface is used instead of Mailbox since it
is based on the Intel Platform Monitoring Technology (PMT) standard.
The Watcher interface provides a more flexible and efficient way to
control and monitor crashlog collection. Hence the functionalities like
rearm and clear are implemented using watcher interface instead of BIOS
mailbox to PUNIT.
Change-Id: I24c5c9753a577b255a7129d20ab83f93001a0485
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88500
Reviewed-by: <srinivas.kulkarni@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
After the BIOS reads and processes the crashLog record, it sets the
CONSUMED_BIOS bit to indicate that the reading and storing of crashlog
record is complete. This is read only bit. When this bit is set ,
crashlog discovery and data collection are skipped. This bit helps in
preventing the same crashLog from being extracted multiple times after
a reset.
BUG= b:None
TEST= The header value during warm boot after crash
cpu_cl_disc_tab.header.data dw0=88420003, dw1=0x0
Change-Id: I4b9e6900218f28b6beb71b7667bc1c57f0134a84
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88499
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
This patch refactors the BMP rendering logic, moving it from
drivers/intel/fsp2_0 to src/lib. This centralizes the code
responsible for rendering BMP images to the framebuffer.
Key changes:
- Move BMP rendering functions (e.g., calculate_logo_coordinates,
copy_logo_to_framebuffer) and their dependencies to
src/lib/render_bmp.c and src/lib/render_bmp.h.
- Decouple BMP definitions from UEFI headers by introducing new
coreboot-specific structures for BMP images and BLT pixels.
- Consolidate bootsplash-related declarations into bootsplash.h,
including new `fw_splash_vertical_alignment`,
`fw_splash_horizontal_alignment`, and `struct logo_config`.
- Update `soc_load_logo_by_coreboot` to use the new common
`load_and_render_logo_to_framebuffer` function and `struct
logo_config` for rendering.
- Relocate `release_logo` to `src/lib/render_bmp.c` for better
module structure.
- Update `src/lib/Makefile.mk` to include the new render_bmp.c.
This refactoring improves code organization and reusability, making
BMP rendering accessible without tight coupling to Intel-specific
driver code.
BUG=b:427387842
TEST=Verify firmware splash screen on google/fatcat.
Change-Id: I0e20ea7e44b4b3ccdb2d4aa9b6aa10ed3447ccfc
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88361
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add wifi SAR table support for kinmen. Bit 2 in the CBI/FW_CONFIG
field is used to determine which SAR table file to load at runtime.
BUG=b:424628935
TEST= check coreboot log:
before:
[WARN ] CBFS: 'wifi_sar_defaults.hex' not found.
[ERROR] Failed to get the wifi_sar_defaults.hex file size!
[ERROR] failed getting SAR limits!
after:
[INFO ] Use wifi_sar_0.hex.
[INFO ] CBFS: Found 'wifi_sar_0.hex' @0x7072c0 size 0x116 in mcache @0x73abdd28
Change-Id: I63e44ba0a4094264165cc9bd7e41c4bd2094c242
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This change adds the necessary configuration for the parade
touchscreen (PRT3406) device, connected to I2C bus 24.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:431658711
TEST=emerge-nissa coreboot and parade touchscreen can work well
Change-Id: I5ca4853c4105d422b907c29fd0b3a4f2a1ce6d9f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Fix resume failure on i2c-ILTK0001:00 where acpi_subsys_resume
returns -121. Increase reset_delay_ms from 10ms to 100ms to
ensure the device is ready after reset.
BUG=b:411164455
TEST=Build and boot and verified resume time across 5 cycles.
All within 500 ms limit.
Suspend-resume time w/ and w/o:
w/o: Average=433.6 ms
1. Resume time 430 ms within limit of 500 ms
2. Resume time 435 ms within limit of 500 ms
3. Resume time 440 ms within limit of 500 ms
4. Resume time 430 ms within limit of 500 ms
5. Resume time 433 ms within limit of 500 ms
w/: Average=449.4 ms
1. Resume time 440 ms within limit of 500 ms
2. Resume time 439 ms within limit of 500 ms
3. Resume time 451 ms within limit of 500 ms
4. Resume time 482 ms within limit of 500 ms
5. Resume time 435 ms within limit of 500 ms
Change-Id: I67ea9aa5ca8ba6f30f772c2decd464d889865347
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88527
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Because when stylus bringing into the garage will resume
from suspend using powerd_dbus_suspend command, so
update the stylus setting which wake_gpe from DW0 to DW2
to fix the funtion.
BUG=b:430712526
BRANCH=none
TEST= Build and boot to OS and check when stylus bringing into
garage and the system will not resume from suspend.
Change-Id: I526b608b03631f365bb33fc44904c87b00a47436
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88479
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Before, the I2C/I3C pads could only be configured to I2C mode. To be
able to use the I3C controller, add the corresponding options and
implementation for the I3C pad mode with all possible voltages.
Change-Id: I1cc2e830019101cfef96b9474477717a8a75111c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This patch supports wake on touch for touchpad when LPSS I2C interface
is used by overriding GPE DW0 with group GPP_F.
Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86
BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.
Change-Id: Id2cc248aacebc0e85d06ad5c63c0605dd72cd05c
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Since the boot flow is different on AMD compared to other x86
platforms document what is done and where.
Explain that AMDCOMPRESS does more than compressing the input.
It also parses the input as an ELF and extracts the first PT_LOAD marked
area from it and discards all other information from the ELF.
Explain bootblock.bin generation and that it has not much to do
with bootblock.elf, unlike on other platforms.
While on it also fix a whitespace in the following line.
Change-Id: Ida763f879c133be54ea1ca2abd3059db0d2c1ef7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87316
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Ensure that only one PT_LOAD segment is inside the input ELF as
the tool only expects and support one PT_LOAD segment. Instead of silently
discarding all other PT_LOAD segments than the first throw an error.
Change-Id: I90cfc8b9dd0b5e8060880790e5ff0ce73843943b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87315
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently we set DP_PHY_DIG_TX_CTL_0 during the PHYD reset flow.
However, that would cause the training to fail and result in
intermittent black screen issues.
As suggested by the eDP PHYD designer, the reset procedure should be
refined by setting bit 0 of DP_PHY_DIG_SW_RST from 0 to 1 to reset the
eDP PHYD status before training. DP_PHY_DIG_TX_CTL_0 controls the eDP
PHYD lane count: setting BIT0 enables lane0, and setting BIT1 enables
lane1. The eDP PHYD designer also recommends that when resetting PHYD,
it is sufficient to set DP_GLB_SW_RST_PHYD and leave DP_PHY_DIG_TX_CTL_0
unchanged.
After this change, this function is identical to the mt8189
implementation. Move dptx_hal_phyd_reset code to common for reuse.
BUG=b:427119942
BRANCH:rauru
TEST=Check the display function on Navi
Change-Id: I07bd6203a2b957eea79d1431953b043820c00338
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88450
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
