mb/google/skywalker: Initialize clkbuf and srclken in romstage

Initialize clkbuf and srclken drivers.

BUG=b:379008996,b:422503190,b:403478729
BRANCH=none
TEST=1. Check register is configured  correctly:
clkbuf:
[clk_buf_init_pmic_clkbuf] XO_WCN_VOTER(0x7c0)
[clk_buf_init_pmic_clkbuf] XO_NFC_VOTER(0x1)
[clk_buf_init_pmic_clkbuf] XO_CEL_VOTER(0x7c0)
[clk_buf_init_pmic_clkbuf] XO_EXT_VOTER(0x1)
srclken:
RG_CENTRAL_CFG1: 0x104014e5
RG_CENTRAL_CFG2: 0x1010
RG_CENTRAL_CFG3: 0x400f
RG_CENTRAL_CFG4: 0x2020800
RG_CENTRAL_CFG5: 0x1bfc1761
RG_CENTRAL_CFG6: 0x0
2. Pass Y1_PMIC MT6365-26MHz cystal test.

Signed-off-by: LiLiang Chen <liliang.chen@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I9fe79a9f457f3e2efd2e810b87ea91c92ddd69b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
LiLiang Chen 2025-06-08 22:55:40 +08:00 committed by Yu-Ping Wu
commit 4b6ebbdd94

View file

@ -2,6 +2,7 @@
#include <arch/stages.h>
#include <delay.h>
#include <soc/clkbuf_ctl.h>
#include <soc/dvfs.h>
#include <soc/emi.h>
#include <soc/mt6315.h>
@ -10,6 +11,7 @@
#include <soc/pmif.h>
#include <soc/regulator.h>
#include <soc/rtc.h>
#include <soc/srclken_rc.h>
#include <soc/thermal.h>
static void raise_little_cpu_freq(void)
@ -30,5 +32,7 @@ void platform_romstage_main(void)
rtc_boot();
dvfs_init();
mtk_dram_init();
srclken_rc_init();
clk_buf_init();
thermal_init();
}