mb/google/skywalker: Initialize clkbuf and srclken in romstage
Initialize clkbuf and srclken drivers. BUG=b:379008996,b:422503190,b:403478729 BRANCH=none TEST=1. Check register is configured correctly: clkbuf: [clk_buf_init_pmic_clkbuf] XO_WCN_VOTER(0x7c0) [clk_buf_init_pmic_clkbuf] XO_NFC_VOTER(0x1) [clk_buf_init_pmic_clkbuf] XO_CEL_VOTER(0x7c0) [clk_buf_init_pmic_clkbuf] XO_EXT_VOTER(0x1) srclken: RG_CENTRAL_CFG1: 0x104014e5 RG_CENTRAL_CFG2: 0x1010 RG_CENTRAL_CFG3: 0x400f RG_CENTRAL_CFG4: 0x2020800 RG_CENTRAL_CFG5: 0x1bfc1761 RG_CENTRAL_CFG6: 0x0 2. Pass Y1_PMIC MT6365-26MHz cystal test. Signed-off-by: LiLiang Chen <liliang.chen@mediatek.corp-partner.google.com> Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com> Change-Id: I9fe79a9f457f3e2efd2e810b87ea91c92ddd69b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/88526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@ -2,6 +2,7 @@
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#include <arch/stages.h>
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#include <delay.h>
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#include <soc/clkbuf_ctl.h>
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#include <soc/dvfs.h>
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#include <soc/emi.h>
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#include <soc/mt6315.h>
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@ -10,6 +11,7 @@
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#include <soc/pmif.h>
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#include <soc/regulator.h>
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#include <soc/rtc.h>
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#include <soc/srclken_rc.h>
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#include <soc/thermal.h>
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static void raise_little_cpu_freq(void)
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@ -30,5 +32,7 @@ void platform_romstage_main(void)
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rtc_boot();
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dvfs_init();
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mtk_dram_init();
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srclken_rc_init();
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clk_buf_init();
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thermal_init();
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}
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