erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/gigabyte: Add ga-h81m-d2w (ITE8620E superio)

Browse source 
This board came virtually rebranded from a specific German OEM called
Wortmann AG and was identified as "TERRA_PC/H81M-D2W" model: 1009381.
It however ships a GIGABYTE GA-H81M-D2W rev 1.0 branded motherboard
which is extremely similar to a Retail GIGABYTE GA-H81M-D2V rev 1.0.
The only obvious differences are the onboard video outputs, its serial
connectivity and total abscence of it on the GIGABYTE support website.

- GA-H81M-D2W
    DVI-D + DVI-I + serial port header on motherboard
- GA-H81M-D2V
    DVI-D + VGA + DB9 serial port connector on backplate

Mainboard: GIGABYTE GA-H81M-D2W rev 1.0

Pure autoport (initial commit) doesn't boot, second patch brings up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, PCIe fixes enabling onboard LAN and other PCIe slots
and some IT8625E superio code from a other coreboot port made most
ITE8620E superio related functions work, especially WDT otherwise this
board resets every couple of seconds! Autoport did log hda codec / pins
but it didn't include them in the hda_verb.c, so I added them manually
which also fixes pcspkr (beep codes, not soundcard connected).

Flash instructions:
Internal flashing using flashrom works on OEM and when running coreboot
using the following command: flashrom -p internal -c "MX25L6473F" -w ROM
An external flasher ch341a_spi (3.3v mod) used with a SOIC 8 pomona
probe to recover the MX25L6473F in situ also works without issues. Only
the power of the USB programmer was used, and the board's main PSU was
disconnected during external flash!

Tested:
 - coreboot 25.06-77-g812d0e2f626d as base
 - EDK2 (MrChromebox/2502)
 - SeaBIOS 1.16.3
 - Broadwell mrc.bin (tidus)
 - Haswell mrc.bin (peppy used for all mrc.bin noted testing)
 - Haswell NRI
 - libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
 - DVI-D & DVI-I (VGA) all work during POST, BOOT and OS
 - Pentium G3220 / Xeon E3-1225 v3 / Xeon E3-1231 v3
 - RAM single and dual slot 2GB/4GB/8GB mixed DDR3 DIMMS max 6, 8, 16GB
	(NRI & mrc.bin)
	0/2: 2GB DDR3-1333 - Kingston 99U5458-001.A00LF (2010-W29)
	0&2: 4GB DDR3-1600 - Kingston 9905402-174.A00G (2015-W33)
	0/2: 2GB DDR3-1600 - Micron 8JTF25664AZ-1G6M1 (2013-W37)
	0/2: 4GB DDR3-1600 - Samsung M378B5173BH0-CK0 (2013-W30)
	(NRI single DIMM won't mix with others)
	0/2: 8GB DDR3-1600 - SK Hynix HMT41GU6MFR8C-PB (2023-W20)
	(ECC UDIMM, mrc.bin only, see NRI note below)
	0&2: 4GB DDR3-1600 ECC - Kingston 9965432-051.A00LF (2013-W19)
	0&2: 8GB DDR3-1866 ECC - Micron 18JSF1G72AZ-1G9E1 (2013-W29)
 - Fedora MATE 42 (Kernel 6.14)
 - KDE NEON 6.4 (Kernel 6.11)
 - MS Windows 10 / 11
 - Audio Outputs both DVI > HDMI, Headphone, Line Out (left&right chan.)
 - Audio Input Line In (back)
 - pcspkr
 - USB2/3 all Intel ports
 - SATA 4 ports
 - PCIe slots (16x 5GT/s & both 1x 5GT/s)
 - iGPU (plus dGPU as in dual GPU work both with mrc.bin / Haswell NRI)
 - dGPU (nVidia GeForce GT640-2GD3 2.5GT/s / Radeon HD7770-1GB 5GT/s)
 - Realtek RTL8111F onboard Gb LAN
 - Wake on LAN
 - HWM shows both fan speeds and voltages
 - PS/2 port (both Keyboard and Mouse with Y splitter cable)
 - Serial port header (coreboot console & OS)
 - PowerButton (Poweron/Poweroff/Wake)
 - ResetButton
 - LEDs HDD & POWER (off during suspend)
 - Shutdown/Reboot/Suspend
 - Strip down the Intel ME/TXE firmware (make menuconfig) see ME note!
 - Disabling ME HECI (manually remove from devicetree.cb) see ME note!
 - flashrom -p internal -c "MX25L6473F" #read & write

Not tested:
 - Audio Inputs Front & Back Microphone Ports
 - parallel port header
 - USBDEBUG
 - VBIOS

Not working:
 - Disable Intel ME PCI interface (make menuconfig)
 - USB2/3 all VIA VL805 backpanel ports

FD layout note:
The original OEM firmware ships a BIOS region that seem to use the
whole firmware:

00000000:00000fff fd
00000000:007fffff bios
00001000:001fffff me

Although coreboot works fine with this flash descriptor layout it is
mandatory to flash a complete image! Replacing only a specific region
like the BIOS region when relying on --ifd will confuse flashrom and
trash the flash chip's contents! As a temporary measure one can use
--layout to flash a specific region using the following layout:

00000000:00000fff fd
00001000:001fffff me
00200000:007fffff bios

Permanently changing the flash descriptor layout to look like this will
solve flashing specific regions and remains a valid option since it
cannot break GIGABYTE its DualBIOS feature since its absent.

NRI note:
EDK2 shows 0GB instead of the actual RAM amount installed. While using
Haswell mrc.bin EDK2 shows the correct amount of RAM. The earlier noted
RAM modules have also been tested using NRI in Memtest86+ v7.20 which
still correctly displays and test the total amount of RAM.
ECC UDIMMs currently do not work on this board because NRI does
not check whether the board / chipset support ECC. This results
in RCVET failures for the ECC bytelane (byte 8). Eventually this
will be fixed in NRI. Haswell mrc.bin works as expected.

ME note:
Neutering the ME will let the system still function correctly, unless
you include EFFS and FCRS partitions addressed by ME_CLEANER_ARGS:

"-S --whitelist EFFS,FCRS"

Failing to supply these ME partitions will cripple superio functions as
in serial output (breaks coreboot serial console) and HWM fan and
voltage info goes random nuts while the fan stays at normal speed.

VIA VL805 note:
Without firmware loading (which is still unknown) and enabling it in the
devicetree.cb will give DMAR IOMMU errors therefore disabled by default!

The data.vbt blob was extracted using debugfs from the OEM F5 firmware
which enables both video outputs DVI-D and DVI-I (VGA).

Since this board is not listed on the GIGABYTE website, but it works
with the Retail GA-H81M-D2V F6 firmware I listed that one instead in the
board_info.txt. However I cannot confirm that this coreboot port also
works for the GA-H81M-D2V, it is good practice to at least check its
gpio values matching this port!

Change-Id: I80dc414a92d115099ec8966841af0cf22d5b1d09
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88412
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Walter Sonius 2025-07-12 16:11:23 +02:00 • committed by Angel Pons
commit eeb15e83cb
15 changed files with 487 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

32
src/mainboard/gigabyte/ga-h81m-d2w/Kconfig Normal file
View file

@ -0,0 +1,32 @@
## SPDX-License-Identifier: GPL-2.0-only
if BOARD_GIGABYTE_GA_H81M_D2W
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
select CPU_INTEL_HASWELL
select GFX_GMA_ANALOG_I2C_HDMI_B
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_GMA_HAVE_VBT
select MAINBOARD_HAS_LIBGFXINIT
select NORTHBRIDGE_INTEL_HASWELL
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_LYNXPOINT
select SUPERIO_ITE_IT8625E
config MAINBOARD_DIR
default "gigabyte/ga-h81m-d2w"
config MAINBOARD_PART_NUMBER
default "GA_H81M_D2W"
config ME_CLEANER_ARGS
depends on USE_ME_CLEANER
default "-S --whitelist EFFS,FCRS"
config USBDEBUG_HCD_INDEX
default 2
endif

4
src/mainboard/gigabyte/ga-h81m-d2w/Kconfig.name Normal file
View file

@ -0,0 +1,4 @@
## SPDX-License-Identifier: GPL-2.0-only
config BOARD_GIGABYTE_GA_H81M_D2W
bool "GA_H81M_D2W"

6
src/mainboard/gigabyte/ga-h81m-d2w/Makefile.mk Normal file
View file

@ -0,0 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += bootblock.c
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

3
src/mainboard/gigabyte/ga-h81m-d2w/acpi/ec.asl Normal file
View file

@ -0,0 +1,3 @@
/* SPDX-License-Identifier: CC-PDDC */
/* Please update the license if adding licensable material. */

10
src/mainboard/gigabyte/ga-h81m-d2w/acpi/platform.asl Normal file
View file

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Method(_WAK, 1)
{
Return(Package() {0, 0})
}
Method(_PTS, 1)
{
}

3
src/mainboard/gigabyte/ga-h81m-d2w/acpi/superio.asl Normal file
View file

@ -0,0 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/pc80/pc/ps2_controller.asl>

8
src/mainboard/gigabyte/ga-h81m-d2w/board_info.txt Normal file
View file

@ -0,0 +1,8 @@
Category: desktop
Board URL: https://www.gigabyte.com/Motherboard/GA-H81M-D2V-rev-10
ROM IC: MX25L6473F
ROM protocol: SPI
Flashrom support: y
ROM package: SOIC8
ROM socketed: no
Release year: 2014

16
src/mainboard/gigabyte/ga-h81m-d2w/bootblock.c Normal file
View file

@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/lynxpoint/pch.h>
#include <device/pnp_ops.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8625e/it8625e.h>
#define UART_DEV PNP_DEV(0x2e, 0x1)
#define SIO_GPIO PNP_DEV(0x2e, IT8625E_GPIO)
void mainboard_config_superio(void)
{
ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot
}

BIN
src/mainboard/gigabyte/ga-h81m-d2w/data.vbt Normal file
View file

Binary file not shown.

97
src/mainboard/gigabyte/ga-h81m-d2w/devicetree.cb Normal file
View file

@ -0,0 +1,97 @@
chip northbridge/intel/haswell
register "gpu_ddi_e_connected" = "1"
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"
register "spd_addresses" = "{0x50, 0, 0x52, 0}"
chip cpu/intel/haswell
device cpu_cluster 0 on ops haswell_cpu_bus_ops end
end
device domain 0 on
ops haswell_pci_domain_ops
device pci 00.0 on # Host bridge
subsystemid 0x1458 0x5000
end
device pci 01.0 on # PCIEX16
subsystemid 0x1458 0x5000
end
device pci 02.0 on # Internal graphics VGA controller
subsystemid 0x1458 0xd000
end
device pci 03.0 on end # Mini-HD audio
chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
register "gen1_dec" = "0x003c0a01"
register "gpe0_en_1" = "0x20000246"
register "sata_port0_gen3_dtle" = "0x2"
register "sata_port1_gen3_dtle" = "0x2"
register "sata_port_map" = "0x33"
device pci 14.0 on # xHCI Controller
subsystemid 0x1458 0x5007
end
device pci 16.0 on # Management Engine Interface 1
subsystemid 0x1458 0x1c3a
end
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on # USB2 EHCI #2
subsystemid 0x1458 0x5006
end
device pci 1b.0 on # High Definition Audio
subsystemid 0x1458 0xa002
end
device pci 1c.0 on # PCIe Port #1
subsystemid 0x1458 0x5001
end
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 on # PCIe Port #3: Realtek RTL8111F GbE NIC
subsystemid 0x1458 0x5001
device pci 00.0 on end
end
device pci 1c.3 off # PCIe Port #4: VIA VL805 USB
subsystemid 0x1458 0x5001
end
device pci 1c.4 on # PCIEX1_1
subsystemid 0x1458 0x5001
end
device pci 1c.5 on # PCIEX1_2
subsystemid 0x1458 0x5001
end
device pci 1d.0 on # USB2 EHCI #1
subsystemid 0x1458 0x5006
end
device pci 1f.0 on # LPC bridge
subsystemid 0x1458 0x5001
chip superio/ite/it8625e
device pnp 2e.1 on # COM
io 0x60 = 0x03f8
irq 0x70 = 0x04
irq 0xf1 = 0x50
end
device pnp 2e.4 on # EC
io 0x60 = 0x0a30
irq 0x70 = 9
io 0x62 = 0x0230
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x0060
irq 0x70 = 1
io 0x62 = 0x0064
end
device pnp 2e.6 on # Mouse
irq 0x70 = 12
end
device pnp 2e.7 off end # GPIO
end
end
device pci 1f.2 on # SATA Controller (AHCI)
subsystemid 0x1458 0xb005
end
device pci 1f.3 on # SMBus
subsystemid 0x1458 0x5001
end
device pci 1f.5 off end # SATA Controller (Legacy)
device pci 1f.6 off end # Thermal
end
end
end

27
src/mainboard/gigabyte/ga-h81m-d2w/dsdt.asl Normal file
View file

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20141018
)
{
#include <acpi/dsdt_top.asl>
#include "acpi/platform.asl"
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/common/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
Device (\_SB.PCI0)
{
#include <northbridge/intel/haswell/acpi/hostbridge.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
}
}

17
src/mainboard/gigabyte/ga-h81m-d2w/gma-mainboard.ads Normal file
View file

@ -0,0 +1,17 @@
-- SPDX-License-Identifier: GPL-2.0-or-later
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(HDMI1,
HDMI2,
Analog,
others => Disabled);
end GMA.Mainboard;

201
src/mainboard/gigabyte/ga-h81m-d2w/gpio.c Normal file
View file

@ -0,0 +1,201 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio2 = GPIO_MODE_GPIO,
.gpio3 = GPIO_MODE_GPIO,
.gpio4 = GPIO_MODE_GPIO,
.gpio5 = GPIO_MODE_GPIO,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_NATIVE,
.gpio10 = GPIO_MODE_NATIVE,
.gpio11 = GPIO_MODE_GPIO,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_NATIVE,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_NATIVE,
.gpio19 = GPIO_MODE_GPIO,
.gpio20 = GPIO_MODE_NATIVE,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_GPIO,
.gpio23 = GPIO_MODE_NATIVE,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_NATIVE,
.gpio26 = GPIO_MODE_NATIVE,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_NATIVE,
.gpio30 = GPIO_MODE_NATIVE,
.gpio31 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio2 = GPIO_DIR_INPUT,
.gpio3 = GPIO_DIR_INPUT,
.gpio4 = GPIO_DIR_INPUT,
.gpio5 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_OUTPUT,
.gpio11 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_OUTPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_OUTPUT,
.gpio22 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_OUTPUT,
.gpio31 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio8 = GPIO_LEVEL_HIGH,
.gpio12 = GPIO_LEVEL_HIGH,
.gpio13 = GPIO_LEVEL_HIGH,
.gpio15 = GPIO_LEVEL_LOW,
.gpio21 = GPIO_LEVEL_LOW,
.gpio24 = GPIO_LEVEL_LOW,
.gpio28 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
.gpio24 = GPIO_RESET_RSMRST,
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio11 = GPIO_INVERT,
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_GPIO,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio40 = GPIO_MODE_NATIVE,
.gpio41 = GPIO_MODE_NATIVE,
.gpio42 = GPIO_MODE_NATIVE,
.gpio43 = GPIO_MODE_NATIVE,
.gpio44 = GPIO_MODE_NATIVE,
.gpio45 = GPIO_MODE_NATIVE,
.gpio46 = GPIO_MODE_NATIVE,
.gpio47 = GPIO_MODE_NATIVE,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_GPIO,
.gpio51 = GPIO_MODE_GPIO,
.gpio52 = GPIO_MODE_GPIO,
.gpio53 = GPIO_MODE_GPIO,
.gpio54 = GPIO_MODE_GPIO,
.gpio55 = GPIO_MODE_GPIO,
.gpio56 = GPIO_MODE_NATIVE,
.gpio57 = GPIO_MODE_GPIO,
.gpio58 = GPIO_MODE_NATIVE,
.gpio59 = GPIO_MODE_NATIVE,
.gpio60 = GPIO_MODE_NATIVE,
.gpio61 = GPIO_MODE_NATIVE,
.gpio62 = GPIO_MODE_NATIVE,
.gpio63 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_OUTPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_INPUT,
.gpio35 = GPIO_DIR_OUTPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio50 = GPIO_DIR_INPUT,
.gpio51 = GPIO_DIR_OUTPUT,
.gpio52 = GPIO_DIR_INPUT,
.gpio53 = GPIO_DIR_OUTPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio55 = GPIO_DIR_OUTPUT,
.gpio57 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio33 = GPIO_LEVEL_HIGH,
.gpio35 = GPIO_LEVEL_LOW,
.gpio51 = GPIO_LEVEL_HIGH,
.gpio53 = GPIO_LEVEL_HIGH,
.gpio55 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_NATIVE,
.gpio65 = GPIO_MODE_NATIVE,
.gpio66 = GPIO_MODE_NATIVE,
.gpio67 = GPIO_MODE_NATIVE,
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio70 = GPIO_MODE_NATIVE,
.gpio71 = GPIO_MODE_NATIVE,
.gpio72 = GPIO_MODE_GPIO,
.gpio73 = GPIO_MODE_NATIVE,
.gpio74 = GPIO_MODE_NATIVE,
.gpio75 = GPIO_MODE_NATIVE,
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio72 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
};
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};

28
src/mainboard/gigabyte/ga-h81m-d2w/hda_verb.c Normal file
View file

@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x10ec0887, /* Codec Vendor / Device ID: Realtek */
0x1458a002, /* Subsystem ID */
15, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(0, 0x1458a002),
AZALIA_PIN_CFG(0, 0x11, 0x4037c040),
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x14, 0x01014010),
AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
AZALIA_PIN_CFG(0, 0x19, 0x02a19040),
AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1d, 0x4024c601),
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

35
src/mainboard/gigabyte/ga-h81m-d2w/romstage.c Normal file
View file

@ -0,0 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void)
{
}
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* FIXME: Length and Location are computed from IOBP values, may be inaccurate */
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_FLEX },
{ 0x0040, 1, 0, USB_PORT_FLEX },
{ 0x0110, 1, 1, USB_PORT_BACK_PANEL },
{ 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX },
{ 0x0040, 1, 2, USB_PORT_FLEX },
{ 0x0040, 1, 3, USB_PORT_FLEX },
{ 0x0040, 1, 3, USB_PORT_FLEX },
{ 0x0110, 1, 4, USB_PORT_BACK_PANEL },
{ 0x0110, 1, 4, USB_PORT_BACK_PANEL },
{ 0x0140, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0140, 1, 5, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 6, USB_PORT_FLEX },
{ 0x0040, 1, 6, USB_PORT_FLEX },
};
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, 1 },
{ 1, 1 },
{ 1, 2 },
{ 1, 2 },
};