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sb/intel: Convert set_gpio to gpio_set

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Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.

Migrate all users of the old function to the new function.

Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.

Change-Id: I8c83b3436818275958cd8eb8b1c0d7b235e0344c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88504
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2025-07-13 19:03:47 +02:00 • committed by Matt DeVillier
commit 84899e6fb7
15 changed files with 36 additions and 44 deletions
Download patch file Download diff file Expand all files Collapse all files

9
src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c
View file

@ -4,7 +4,6 @@
#include <device/device.h>
#include <gpio.h>
#include <option.h>
#include <southbridge/intel/common/gpio.h>
#include "chip.h"
/*
@ -32,22 +31,22 @@ static void lenovo_hybrid_graphics_enable(struct device *dev)
" Switching panel to discrete GPU.\n");
if (config->has_panel_hybrid_gpio)
set_gpio(config->panel_hybrid_gpio,
gpio_set(config->panel_hybrid_gpio,
!config->panel_integrated_lvl);
if (config->has_backlight_gpio)
set_gpio(config->backlight_gpio,
gpio_set(config->backlight_gpio,
!config->backlight_integrated_lvl);
} else {
printk(BIOS_DEBUG, "Hybrid graphics:"
" Switching panel to integrated GPU.\n");
if (config->has_panel_hybrid_gpio)
set_gpio(config->panel_hybrid_gpio,
gpio_set(config->panel_hybrid_gpio,
config->panel_integrated_lvl);
if (config->has_backlight_gpio)
set_gpio(config->backlight_gpio,
gpio_set(config->backlight_gpio,
config->backlight_integrated_lvl);
}
}

5
src/drivers/lenovo/hybrid_graphics/romstage.c
View file

@ -6,7 +6,6 @@
#include <option.h>
#include <gpio.h>
#include <types.h>
#include <southbridge/intel/common/gpio.h>
#include "hybrid_graphics.h"
#include "chip.h"
@ -67,10 +66,10 @@ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
*/
if (config->has_dgpu_power_gpio) {
if (*enable_peg)
set_gpio(config->dgpu_power_gpio,
gpio_set(config->dgpu_power_gpio,
!config->dgpu_power_off_lvl);
else
set_gpio(config->dgpu_power_gpio,
gpio_set(config->dgpu_power_gpio,
config->dgpu_power_off_lvl);
} else if (config->has_thinker1) {
bool power_en = pmh7_dgpu_power_state();

4
src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c
View file

@ -5,10 +5,10 @@
#include <device/pnp_ops.h>
#include <device/pci_ops.h>
#include <device/pci.h>
#include <gpio.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <console/console.h>
#include <option.h>
@ -85,7 +85,7 @@ void bootblock_mainboard_init(void)
}
/* Match GPIO to soft strap. */
set_gpio(46, gp46);
gpio_set(46, gp46);
}
void bootblock_mainboard_early_init(void)

11
src/mainboard/google/auron/smihandler.c
View file

@ -2,11 +2,12 @@
#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
#include <soc/pm.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include <gpio.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include "ec.h"
#include <variant/onboard.h>
@ -21,14 +22,14 @@ static void mainboard_disable_gpios(void)
{
#if CONFIG(BOARD_GOOGLE_SAMUS)
/* Put SSD in reset to prevent leak */
set_gpio(BOARD_SSD_RESET_GPIO, 0);
gpio_set(BOARD_SSD_RESET_GPIO, 0);
/* Disable LTE */
set_gpio(BOARD_LTE_DISABLE_GPIO, 0);
gpio_set(BOARD_LTE_DISABLE_GPIO, 0);
#else
set_gpio(BOARD_PP3300_CODEC_GPIO, 0);
gpio_set(BOARD_PP3300_CODEC_GPIO, 0);
#endif
/* Prevent leak from standby rail to WLAN rail */
set_gpio(BOARD_WLAN_DISABLE_GPIO, 0);
gpio_set(BOARD_WLAN_DISABLE_GPIO, 0);
}
void mainboard_smi_sleep(u8 slp_typ)

8
src/mainboard/google/auron/variants/samus/variant.c
View file

@ -2,13 +2,13 @@
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include <gpio.h>
#include <mainboard/google/auron/variant.h>
#include <soc/pm.h>
#include <soc/romstage.h>
#include <smbios.h>
#include <variant/board_version.h>
#include <variant/onboard.h>
#include <mainboard/google/auron/variant.h>
const char *smbios_mainboard_version(void)
{
@ -29,11 +29,11 @@ void mainboard_post_raminit(const int s3resume)
printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());
/* Bring SSD out of reset */
set_gpio(BOARD_SSD_RESET_GPIO, 1);
gpio_set(BOARD_SSD_RESET_GPIO, 1);
/*
* Enable PP3300_AUTOBAHN_EN after initial GPIO setup
* to prevent possible brownout.
*/
set_gpio(BOARD_PP3300_AUTOBAHN_GPIO, 1);
gpio_set(BOARD_PP3300_AUTOBAHN_GPIO, 1);
}

3
src/mainboard/google/jecht/smihandler.c
View file

@ -2,6 +2,7 @@
#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
#include <gpio.h>
#include <soc/pm.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include <soc/iomap.h>
@ -21,7 +22,7 @@ void mainboard_smi_sleep(u8 slp_typ)
/* Enable DCP mode */
if (CONFIG(BOARD_GOOGLE_TIDUS)) {
set_gpio(GPIO_USB_CTL_1, 0);
gpio_set(GPIO_USB_CTL_1, 0);
}
break;
case ACPI_S5:

16
src/mainboard/google/slippy/smihandler.c
View file

@ -1,12 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <northbridge/intel/haswell/haswell.h>
#include <cpu/intel/haswell/haswell.h>
#include <cpu/x86/smm.h>
#include <gpio.h>
#include <northbridge/intel/haswell/haswell.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/me.h>
/* Include EC functions */
#include <ec/google/chromeec/smm.h>
@ -35,10 +35,10 @@ void mainboard_smi_sleep(u8 slp_typ)
case ACPI_S4:
case ACPI_S5:
/* Prevent leak from standby rail to WLAN rail in S3/S4/S5. */
set_gpio(GPIO_WLAN_DISABLE_L, 0);
set_gpio(GPIO_PP3300_CODEC_EN, 0);
gpio_set(GPIO_WLAN_DISABLE_L, 0);
gpio_set(GPIO_PP3300_CODEC_EN, 0);
/* Disable LTE */
set_gpio(GPIO_LTE_DISABLE_L, 0);
gpio_set(GPIO_LTE_DISABLE_L, 0);
break;
}

3
src/mainboard/lenovo/t400/romstage.c
View file

@ -4,7 +4,6 @@
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <gpio.h>
#include <northbridge/intel/gm45/gm45.h>
#include <southbridge/intel/common/gpio.h>
static void hybrid_graphics_init(sysinfo_t *sysinfo)
{
@ -44,5 +43,5 @@ void mb_post_raminit_setup(void)
{
/* FIXME: make a proper SMBUS mux support. */
/* Set the SMBUS mux to the eeprom */
set_gpio(42, GPIO_LEVEL_LOW);
gpio_set(42, GPIO_LEVEL_LOW);
}

4
src/mainboard/lenovo/x200/romstage.c
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
#include <gpio.h>
#include <northbridge/intel/gm45/gm45.h>
void get_mb_spd_addrmap(u8 spd_addrmap[4])
@ -13,5 +13,5 @@ void mb_post_raminit_setup(void)
{
/* FIXME: make a proper SMBUS mux support. */
/* Set the SMBUS mux to the eeprom */
set_gpio(42, GPIO_LEVEL_LOW);
gpio_set(42, GPIO_LEVEL_LOW);
}

5
src/mainboard/lenovo/x200/variants/x200/dock.c
View file

@ -3,7 +3,6 @@
#include <console/console.h>
#include <device/device.h>
#include <gpio.h>
#include <southbridge/intel/common/gpio.h>
#include <ec/lenovo/h8/h8.h>
#include <ec/acpi/ec.h>
@ -22,13 +21,13 @@ void h8_mb_init(void)
void dock_connect(void)
{
ec_set_bit(0x02, 0);
set_gpio(28, GPIO_LEVEL_HIGH);
gpio_set(28, GPIO_LEVEL_HIGH);
}
void dock_disconnect(void)
{
ec_clr_bit(0x02, 0);
set_gpio(28, GPIO_LEVEL_LOW);
gpio_set(28, GPIO_LEVEL_LOW);
}
int dock_present(void)

7
src/mainboard/lenovo/x201/dock.c
View file

@ -3,10 +3,9 @@
#include <console/console.h>
#include <device/device.h>
#include <gpio.h>
#include "dock.h"
#include <southbridge/intel/common/gpio.h>
#include <ec/lenovo/h8/h8.h>
#include <ec/acpi/ec.h>
#include "dock.h"
void h8_mb_init(void)
{
@ -24,7 +23,7 @@ void dock_connect(void)
ec_set_bit(0x1a, 0);
ec_set_bit(0xfe, 4);
set_gpio(28, GPIO_LEVEL_HIGH);
gpio_set(28, GPIO_LEVEL_HIGH);
}
void dock_disconnect(void)
@ -33,7 +32,7 @@ void dock_disconnect(void)
ec_clr_bit(0x1a, 0);
ec_clr_bit(0xfe, 4);
set_gpio(28, GPIO_LEVEL_LOW);
gpio_set(28, GPIO_LEVEL_LOW);
}
int dock_present(void)

2
src/southbridge/intel/common/gpio.c
View file

@ -105,7 +105,7 @@ int gpio_get(gpio_t gpio_num)
/*
* set gpio output to level.
*/
void set_gpio(int gpio_num, int value)
void gpio_set(gpio_t gpio_num, int value)
{
static const int gpio_reg_offsets[] = {
GP_LVL, GP_LVL2, GP_LVL3

2
src/southbridge/intel/common/gpio.h
View file

@ -151,8 +151,6 @@ extern const struct pch_gpio_map mainboard_gpio_map;
/* Configure GPIOs with mainboard provided settings */
void setup_pch_gpios(const struct pch_gpio_map *gpio);
void set_gpio(int gpio_num, int value);
void clear_gpio(int gpio_num);
int gpio_is_native(int gpio_num);

2
src/southbridge/intel/lynxpoint/lp_gpio.c
View file

@ -110,7 +110,7 @@ int gpio_get(gpio_t gpio_num)
return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
}
void set_gpio(int gpio_num, int value)
void gpio_set(gpio_t gpio_num, int value)
{
u16 gpio_base = get_gpio_base();
u32 conf0;

3
src/southbridge/intel/lynxpoint/lp_gpio.h
View file

@ -157,9 +157,6 @@ struct pch_lp_gpio_map {
/* Configure GPIOs with mainboard provided settings */
void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
/* Set GPIO pin value */
void set_gpio(int gpio_num, int value);
/* Return non-zero if gpio is set to native function. 0 otherwise. */
int gpio_is_native(int gpio_num);