The MTE_TAG_ADDR macro is no longer used after the changes in CB:90144.
Remove the unused definition.
BUG=b:438666196
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a --clean
BRANCH=none
Change-Id: Ic71fa22292793162de882d3c764e7805301250c5
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The following error will be shown on non-NVMe SKUs.
[ERROR] DOMAIN: 00000000 missing read_resources
That's because when mainboard_needs_pcie_init() returns false, dev->ops
will be NULL, causing the '!curdev->ops || !curdev->ops->read_resources'
check to fail in device/device.c read_resources().
To prevent the misleading error message from showing up, for non-NVMe
SKUs, assign 'noop_domain_ops' to dev->ops.
BUG=none
TEST=emerge-tanjiro coreboot
BRANCH=rauru
Change-Id: If0f81aadda3fbde99f4df794cbdd885a607c9625
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90843
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This makes it runtime configurable; disabling it can save around
100ms boot time.
Change-Id: I9cddb07fc2e7caf754fa8d665249536c4885a4fe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89918
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
More complex systems, such as servers, have multiple IOMMUs. For
example, Turin CPUs have a total of 4 IOMMUs per socket. Abort IVHD
generation only if IOMMU is not present on domain 0. For other domains
simply continue the loop, so that other domains have their IOMMUs
described properly in the IVRS. To keep simple systems working as
before, IVHD generation is aborted, if IOMMU is not present in domain 0.
TEST=See IOMMUs on domains 1,3,4,6 being skipped during IVHD generation
instead of IVHD generation being aborted on domain 1 on
Gigabyte MZ33-AR1 console log.
Change-Id: Icd3a51621908dc3ee5c85aa1e5814f3b3ac69007
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89111
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On AMD glinda up to 3 CS# lines are available. Drive the correct
SPI flash chip select using register 0x1d when necessary. This
allows to modifiy the contents of the "backup" SPI flash when
booting from the primary SPI flash.
TEST=Can access backup SPI flash on AMD Glinda SoC.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I446ef54a27c7a29155948cef9219cdef7b52b776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The PSP can choose the SPI flash to boot from. One such case
would be a corrupted EFS or invalid PSP directory tables.
Read the active SPI CS index from register SPI_ALT_CS_REG and
use it in boot_device_spi_cs().
Register name is taken from Linux kernel.
TEST=Booted on AMD/glinda with EFS on SPI CS0 corrupted. Will
boot from SPI CS2 and log shows:
spi_init: Booting from SPI CS2
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2c806d4d1563aa2403e84dec9f8768081e5e208a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add verification to ensure that the integrated GPU is available,
avoiding crashes in FSP-M and FSP-S. The problem was first identified
on Skylake systems where the iGPU is missing or disabled, particularly
when VT-D is enabled, which can cause FSP-S to hang during boot.
Enabling SGX hides the issue, but it also leads to unstable
virtualization.
Apply the fix to Alderlake, Cannonlake, and Tigerlake SoCs in addition
to Skylake.
TEST=Build and boot to OS (Windows, Proxmox). Check to verify
functions work. (Skylake H110 + Xeon E3-1245 V5, E3-1260L V5,
i7-6700K, i3-7100)
Change-Id: I394f46ed5a277218a8dd587705eaecabe59fd110
Signed-off-by: Ulysse Ballesteros <ulysseballesteros@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89821
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Relocate the CBMEM top address from a hardcoded 0xC7800000 to the
start of the XBL log region (_dram_xbl_log).
This change moves the CBMEM region from the high Linux Kernel Reserve
block down into the lower DRAM Space 0, adjacent to other firmware
reserved regions. This consolidation prevents marking CBMEM range as
`reserved` and ensures CBMEM is placed in a more stable memory location
(marked available aka System RAM).
- Remove CBMEM_TOP define from addressmap.h.
- Update cbmem_top_chipset() to return (uintptr_t)_dram_xbl_log.
- Update memlayout.ld documentation to reflect the new memory map.
BUG=none
TEST=Boot on X1P42100 platform, verify CBMEM console and tables are
accessible and correctly located via 'cbmem -l'.
w/o this patch:
```
c7800000-cb7fffff : reserved
```
w/ this patch:
```
815a0000-819fffff : System RAM
```
Change-Id: I7392bb7a62d50640696301931940a7baa00351e3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90760
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This reverts commit 292d7b9d3d.
The resume failure is caused by the improper DEVAPC setting in fsp_init
for DM/PM and SPM. If fsp_init runs prior to dpm_init and spm_init, it
requires AP to grant the access to DM/PM and SPM from DEVAPC. The fix is
done in CB:90756.
BUG=b:474254985
TEST=Run suspend/resume test
Change-Id: Id21327f6d65d31659cdb8b4bda3b0a0510c438e8
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The previous implementation used the logical OR (||) operator to select
between config->tdp and get_cpu_tdp(). In C, the || operator returns a
boolean value (0 or 1), not the value of the first true operand. This
caused the function to return incorrect TDP values.
This commit replaces the logical OR with the ternary operator (?:),
ensuring that config->tdp is returned if it is non-zero; otherwise,
get_cpu_tdp() is used. This change restores the intended behavior of
selecting the correct TDP value.
TEST=The power map is properly found and applied on a Panther Lake B005
SoC.
Change-Id: I3a02f804510f87cb4d28bd929869570c355c5242
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90759
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add and enable IOST feature to support Intel's IO Self-Testing Software
(IOST), which is an OS tool for performing electrical margining analysis
on USB4 Host and Device Routers, DP2.1 displays, memory, UFS, and PCIe
Gen4+ devices. This change includes the IOST ACPI device in the SoC's
southbridge ASL and implements the SoC-specific soc_fill_p2sb_ssdt
function used by the common P2SB code to generate ACPI code for enabling
IOST in the DSDT. Additionally, the CBFS option "iost_enable" is
required to enable IOST. Command to add this option to the image:
cbfstool <coreboot_image> add-int -r COREBOOT -i 1 -n option/iost_enable
Note that this cbfstool command is an example, for its syntax format
could be changed in the future versions.
BUG=none
TEST=Build coreboot and add the CBFS option flag to the built image.
Boot to OS and verify IOST can access P2SB registers through the ACPI
interface for electrical margining tests.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I6929fa3a44646c5385199a8b1e3d0b681d36c9cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add ACPI device for Intel's IO Self-Testing Software (IOST), which is an
OS tool for performing electrical margining analysis on USB4 Host and
Device Routers, DP2.1 displays, memory, UFS, and PCIe Gen4+ devices.
This ACPI device provides the necessary P2SB access interface to enable
IOST to interact with hardware registers for comprehensive IO testing
and validation. The ASL file should be included in the SoC's
southbridge.asl.
BUG=none
TEST=Build coreboot with this ASL file included in the SoC's
southbridge.asl. Boot to OS and verify IOST objects appear correctly in
the DSDT tables.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I9417da8322931c2afbf75aa9062bceb52b8320d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90128
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add weak function to fill SSDT for SoC-specific P2SB extensions. SoCs
can implement this function to fill additional P2SB-related ACPI
objects. For instance, a SoC might include the IOST ACPI interface that
uses P2SB and enable it via SSDT for debug purposes at the OS level.
BUG=none
TEST=This change cannot be tested in isolation as it only adds an empty
weak function. Testing requires SoCs to implement the function. Add the
necessary code with the same function name in the SoC to generate ACPI
objects and examine the SSDT for changes after boot.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I352f13b9b05dc4b61608a33c76946883bf0d3de3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add CPUID definition and CPU table entry for Intel Nova Lake processor
(CPUID 0x300f30). This enables basic CPU initialization and
multiprocessor support for Nova Lake platforms
Reference:
- Nova Lake External Design Specification (EDS) Volume 1 (#844316)
BUG=none
Change-Id: Iea89ebfa8bae3448edfb3b757443ec9902cede5e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
The AMD fTPM uses the CRB interface, but doesn't implement all registers
defined in the TCG specification. Add a new driver that deals with the
reduced register set.
The reduced CRB MMIO register space has:
- A START register to ring the doorbell
- An error STATUS register with only one bit
- DMA address and size register for the CRB
- No other status or control registers
- No way to read current locality (assumption is locality 0)
- No interface ID register
- No read only registers
The TPM interface also assumes that the DRTM is always using locality 0.
The fTPM needs to access the SPI flash and this is currently done using
the PSP SMI handler. Thus the fTPM will only operate after SMM has been
set up.
The fTPM needs the PSP directory files type 0x04 and type 0x54. When
the regions are missing or corrupted the fTPM won't be operational.
Based off https://github.com/teslamotors/coreboot/tree/tesla-4.12-amd
TEST=Works on AMD glinda (Fam 1Ah).
This adds the following new log messages:
[DEBUG] PSP: Querying PSP capabilities...OK
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] TPM: CRB buffer created at 0x7b5ee000
[SPEW ] fTPM: CRB TPM initialized successfully
[INFO ] Initialized TPM device fTPM
...
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] TPM2 log created at 0x7b5b1000
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] ACPI: * TPM2
[DEBUG] ACPI: added table 4/32, length now 68
Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88247
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Update the PS1 threshold values for VR_DOMAIN_IA, VR_DOMAIN_GT, and
VR_DOMAIN_SA from 20 A to 15 A, following the recommendations in the
Panther Lake H Platform Design Guide (Draft > 2.1). This change ensures
that power state thresholds are consistent with the most recent platform
specifications, improving accuracy and system behavior under varying
power conditions.
TEST=Fatcat device boots to OS.
Change-Id: I358d4d94c3800ff5b658cb875c90ee7409d86377
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90727
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some payloads such as depthcharge need to run MIPI panel power-off
commands before booting to the kernel. Otherwise, the abnormal power-off
timing would prevent the pixel charge from being cleared before
power-off, leading to the risk of LCD overpotential hence resulting in
image stickiness or flicker upon restarting.
Therefore, add a 'poweroff' field to the panel_serializable_data struct,
which, in a follow-up patch, will be passed to payloads for running the
power-off commands. Each MIPI panel can define the power-off commands in
that field.
As both init and power-off commands are supported, remove "_init" from
related structs and enums.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I1a7c0a14d5c197a0887a26269e4c36e498e8b7ae
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90737
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Move the MIPI panel init command parsing function
mipi_panel_parse_init_commands() and related macros and structs from
drivers/mipi/ to commonlib/mipi/, so that the function can be shared
with payloads.
In a follow-up patch, a 'poweroff' field will be added to the
panel_serializable_data struct and then passed to payloads, so that
payloads can utilize mipi_panel_parse_init_commands() to run the panel
poweroff commands.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I19011669f03d060e9f030b673687cbe5965d7e2f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90736
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Increased MHBR field width in ACPI northbridge.asl from 17 to 27 bits,
allowing MCHBAR to be set above 4GB (up to 42 bits).
Reference: Section 10.3 in 850519
BUG=none
TEST=boot to OS with ACPI debug enabled and check GMHB log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I885ff64598367ddadcec05926af3556024b61250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90729
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This reverts commit 14a7a2315e.
Reason for revert: The change causes DUT failed to resume from S3.
BUG=b:474254985
TEST=Wake up DUT by power key.
Change-Id: I2f2291a12d9b440d000a28e38bb590bc77a02c8a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
The number of MCAX register used inside an MCA BANK changed from phoenix
onwards. Since phoenix all 16 MCAX register are used inside an MCA bank.
According to spec:
The MCA_SYND register stores a syndrome associated with the error logged
in MCA_STATUS or MCA_DESTAT. The “syndrome” may include syndrome values
associated with an error correcting code or other information about the
error. The contents of this register are valid if MCA_STATUS[SYNDV] bit
is set to 1 or MCA_DESTAT[SYNDV] bit is set to 1.
source: AMD64 Architecture Programmers Manual Rev 3.42
Change-Id: I20a31776d4b031c810ef0dc6502c421ade6f4315
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update the SoC USB driver to invoke mainboard_usb_typec_configure for
both primary and secondary ports. This is called after the QMP PHY
initialization to ensure the external signal path is correctly
muxed for the detected orientation.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Sample output:
```
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 00001203 00000000 00000000 00000000 ................
firmware-shell: md 0x0a600420 8
0a600420: 000002a0 00000000 00000000 00000000 ................
0a600430: 00001203 00000000 00000000 00000000 ................
```
Change-Id: Ic90a62b1f6ad62a8870c6d5333d06b6a11d26d4f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90711
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add a function declaration for mainboard_usb_typec_configure. This
allows mainboards to implement custom logic for external components,
such as retimers or muxes, that need orientation-aware configuration.
BUG=b:473489095
TEST=Verify USB SS detection on Quartz.
Change-Id: I20d9a23da5b855a413f8358b8783f44c1632ccdf
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90709
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add spinlock synchronization to prevent concurrent SPI flash controller
access from multiple CPUs in SMP environments. The spinlock serializes
access to the SPI controller hardware in exec_sync_hwseq_xfer().
If SMP is not enabled, spinlock functions are no-ops, so this change
is safe for both SMP and non-SMP configurations.
This resolves an issue seen on the Starlabs Starfighter MTL where
multiple SPI transaction errors occurred when reading option variables
stored in SMMSTORE:
[ERROR] SPI Transaction Error at Flash Offset 103002a HSFSTS = 0x01016022
[ERROR] SPI Transaction Error at Flash Offset 1030004 HSFSTS = 0x01006022
[ERROR] SPI Transaction Error at Flash Offset 1030000 HSFSTS = 0x3f006022
...
Change-Id: Ic3003b0a986b587622102b6f36714bcb16c3d976
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Refactor code to use less redundant PCI accesses to decrease boot time.
Change-Id: Ic2bb610ebf22dd43580ac94360d905b1c782224a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90641
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor fsp_init to be called as a boot state entry
(BS_DEV_INIT, BS_ON_ENTRY) instead of directly from soc_init. This
ensures fsp initialization occurs at the appropriate boot stage.
This change is necessary for FW logo rendering in the ramstage. fsp_init
must be run before FW display starts rendering the logo.
BUG=b:471111147
TEST=Check FW logo
Change-Id: I41b32229d4c582d84afac5c336eb98b1b1274ba8
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Starting with Turin there are 8 IOHCs per SoC. Add new definitions
for the missing IOHCs. Based on Turin C1 PPR (doc 57238).
Change-Id: I31e93e680e3f0ba03d2595f632d6827b4e3042b8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90368
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Strip quotes from CONFIG_AMDFW_CONFIG_FILE, otherwise the IF condition
may not catch the case when CONFIG_AMDFW_CONFIG_FILE is an empty string.
TEST=Omit PSP blobs when building coreboot for Gigabyte MZ33-AR1 by
clearing the AMDFW_CONFIG_FILE path.
Change-Id: I1ecf61844c03c89b3429e23936172f79c8d4b2f4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90367
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add PCI I/O-based SMN accessors. These accessors can be used for
early workarounds when the PCI ECAM MMCONF is not working yet.
An example of such workaround is the patching of PCI ECAM MMCONF
base address in Turin SoC, which has to be done via SMN, but it
cannot use PCI ECAM MMCONF to access SMN yet.
Change-Id: I5e0faaa48e4d7b4479e3af9b795ad2a879f569fd
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add API to initialize RPMh resources for display. It includes CMD-DB
initialization, enable the MMCX power rail and cast a vote for the MM0
Bus Clock Manager (BCM) resource to enable display clocks.
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified MMCX rail enablement and MM0 BCM vote using ARC and
BCM AOP dump with API invoking changes hooked up with follow-on
commits.
Serial Log:
[INFO ] RPMH_REG: Initialized mmcx.lvl at addr=0x30080
[INFO ] ARC regulator initialized successfully
[DEBUG] RPMH_REG: Sent active request for mmcx.lvl
[INFO ] ARC level was set successfully
[DEBUG] BCM: Found address 0x00050024 for resource MM0
[INFO ] BCM: Successfully voted for MM0 (addr=0x00050024, val=0x60004001)
[INFO ] BCM vote for MM0 sent successfully
Change-Id: I1997ce7a1ced4504d6a3170e5f2ddd4f52e0763d
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90467
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add RPMh driver support, introducing the core driver that provides
an interface to the RPMh protocol for managing ARC/VRM/BCM type
resource requests. This includes basic TCS (Trigger Command Sets)
handling and helper functions for sending RPMh requests.
RPMh (Resource Power Manager – hardware) is a protocol that enables
processors (e.g., APSS, LPASS) to send power-related commands to the
RPMh hardware block. Dynamic management of power and clocks for shared
resources is handled either directly by hardware or by RPM.
Key features include:
- Core infrastructure for submitting TCS (Trigger Command Sets)
commands to the RPMh.
- Regulator driver using RPMh for LDOs and SMPS control.
- BCM (Bus Clock Manager) voting for clock resources.
Test=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I1f85459c68d0256e15765b0716856dc928080df9
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The display buffer reservation logic has been removed, so the related
symbol declarations are no longer needed.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I873fdcff4071e0d2cf683017557abdfdb13e8b16
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90653
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The display buffer was previously reserved as unavailable by coreboot,
which prevented the kernel from mapping it. When the splash driver
released the buffer, the kernel later crashed on access because the
region was never mapped.
This patch removes the reservation so the kernel can map the display
buffer and reuse it safely.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Check that the display memory region is mapped by kernel in UART logs:
[ 0.000000][ T0] node 0: [mem 0x00000000e36a0000-
0x00000000f7bfffff]
Change-Id: I507d48713690bac3030f81a29c7e123fd3a03b95
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
QCLib passes SHRM metadata to TME for authentication and to bring SHRM
out of reset. In RAM dump mode, this sequence is unnecessary because
the system is preserving state for post-crash analysis.
This patch adds a RAM-dump-mode check and ensures:
- SHRM metadata is not loaded or populated into the interface table
when RAM dump mode is detected, preventing QCLib from sending it to
TME.
Test=Create an image.serial.bin and verify it boots on X1P42100.
Change-Id: I921a2b99543ee462433bec8e8471ad836cabc5dd
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90652
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This power resource is valid in S5, so correct the level that is
set. This makes it match the reference code, and the CNVi Bluetooth
power resource.
Change-Id: I430cafafc0326dc189a337bf2b67cf200afc4f17
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90610
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current code left Bluetooth disabled if it times out during reset.
Following the flow of the reference code, re-enable it to avoid it
ending up "stuck" off.
Change-Id: Ib1c49f28ec13068d9d7e59841ae35d1d26c30770
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90607
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The saved error values were reversed, so correct these.
This isn't a functional change, as the value isn't used in ACPI.
Change-Id: I9d3abcb4b17c36d33f2660e5d20fd5e6fb15fc34
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the value of BIAS_POWER_ON in the MT8189 dptx_reg.h file,
by changing it from 0x01 to 0x03. The MT8189 needs to enable one
more power register bit to make bias work rather than timeout.
BUG=b:461384417
TEST=Boot up can see develop mode.
BRANCH=skywalker
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Change-Id: I345b23af0b5802e71d6d7bcd3fe806aaa71cc3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit introduces ChromeOS-specific logic to the Panther Lake SoC
TDP selection. It addresses the need to correctly set the CPU TDP to 15
W without having to set the desired_tdp flag in each mainboard device
tree.
BUG=b:465698900
Change-Id: Ibaee530159f7e3b94aac16ab50b749cb161cee10
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces a mechanism to configure the Thermal Design Power
(TDP) for Panther Lake, allowing board designers to override the default
TDP reported by hardware and select the value that matches their
specific board requirements.
Previously, the TDP value was determined solely by the hardware, which
limited flexibility for platforms that support multiple TDP options. By
adding a new field to the `soc_intel_pantherlake_config` structure and
implementing the `soc_get_cpu_tdp()` function, this change enables
boards to opt out of the default TDP and specify a custom value.
BUG=b:465698900
Change-Id: I6e401c2c7d7d0cda24fa07ec024813874fac3ed5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90150
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update PL1 override values from a fixed value to zero, indicating that
the platform should use the default TDP value. This change allows the
common code to dynamically set PL1 according to the specific TDP SKU,
improving flexibility and ensuring correct power limit configuration
across different hardware variants.
Previously, PL1 was hardcoded to 15 for some SKUs, which could lead to
instabilities for SKUs with different TDP requirements.
TEST=No instability was observed on certain Fatcat SKUs.
Change-Id: Ibfb6b52aa15ad66740abc39f6f869dfa5e90de3c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89934
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Ryu, Jamie M <jamie.m.ryu@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
The pic_width and pic_height in the dsc_config struct are equivalent to
edid.mode.ha and edid.mode.va. The duplicate information should be
removed from the panel_serializable_data struct, by removing from
dsc_config. To do that, replace references of dsc_config.pic_width with
edid.mode.ha in the MT8196 code.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: Id1014886851a999ccdfec7ec86df2e7341ba9ffd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90560
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
We'd like to replace dsc_cfg->pic_width with edid->mode.ha in MT8196's
dsc_configure_registers() and then deprecate the 'pic_width' field. To
do that, we will first need to pass the edid struct pointer from
mtk_ddp_mode_set() all the way to that function.
Currently mtk_ddp_mode_set() is in the MediaTek common code, which calls
SoC's mtk_ddp_soc_mode_set(), but the edid isn't passed. To simplify the
edid pointer passing, drop mtk_ddp_soc_mode_set() and replace it with
SoC's mtk_ddp_mode_set(). To minimize the duplicate code of calculating
vrefresh, introduce mtk_get_vrefresh() to the display API, and reference
it from SoC's code.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: Ifb84c6b954dde2f25c3ac491a5392b7725c13a43
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90559
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Pass dsi_regs to mtk_dsi_cphy_timing() to be consistent with other DSI
APIs and mtk_dsi_dphy_timing(). This also supports C-PHY with dual
channel, although there is currently no such a device.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: I81805aa181c46fb29c70d18553dbf0c0c06c2888
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90558
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
