This patch unifies all the felino variants based on
`BOARD_GOOGLE_MODEL_FELINO` to use the same mainboard part number
`Felino`.
BUG=b:430205874
TEST=Able to build/boot felino
Change-Id: I15a9372e18a910916e9f695d920fc502bf6afa06
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88611
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When bundled fw is NULL the system boot hangs.
Add a judgement to return mismatch when bundled fw is NULL.
BUG=b:434844512
BRANCH=firmware-brox-16080.B
TEST=emerge-brox coreboot
set FW_CONFIG=STORAGE_NVME and DUT can boot into OS
Change-Id: Ibe81e944725b8c387c61451c2e422d57f7aeb8c1
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The magic number '1' for VgaInitControl is replaced with the
VGA_INIT_CONTROL_ENABLE macro for improved readability and
maintainability.
This makes the code's intent clearer and aligns with best practices
for using named constants.
The VGA_INIT_CONTROL_ENABLE macro is defined in ux.h along with a
comment to describe its purpose.
TEST=Able to see eSOL while booting google/fatcat.
Change-Id: I27a91030c0aaa52e099869c5870da670d3e28628
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Update the verb table to decrease the speaker output level.
BUG=b:404480459
TEST=Build and boot to OS, check test result is pass with
hardware engineer and Realtek.
Change-Id: I4f0544ab220ffdbcb2e61ca2f1d2e0d9ae36b1ce
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88592
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Kaladin support 2 kinds of ELAN touchscreen with different
slave address:
TOP(Touch_IC on Panel): slave address 0x10
DBTS(Touch IC on Daughter BOARD):slave address 0x15
Add FW config to separate ELAN touch screen.
BUG=b:434591789
TEST=build and verified touchscreen work
Change-Id: I3e1c748baf1d392c626ce17f4fcb601ec02ce428
Signed-off-by: wu.garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88585
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit assigns pci_dev_request_bus_master to the .final operation
for both the DSP and HDA device operations to ensure that the bus
master is enabled.
This change ensures correct PCI configuration for DSP and HDA devices,
preventing potential issues with direct memory access operations.
BUG=b:427091370
TEST=Able to build and boot google/fatcat.
w/o this patch
```
firmware-shell: pcir.b 0 0x1f 3 0x4
0x02
```
w/ this patch:
```
firmware-shell: pcir.b 0 0x1f 3 0x4
0x06
```
Change-Id: Id2480dba08ea8ee7a9219327b8a31f8f9f65410c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit transitions the touchscreen power sequencing from static
coreboot GPIO configuration to ACPI-driven management for the Francka
variant.
BUG=b:430444353
TEST=Able to build and boot google/francka. Verified touchscreen is
working as expected with this patch.
Change-Id: I2b6c0cacdc159eaf98279bd57efb81c8454ee580
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
BUG=b:368661724, b:434033860, b:407590653, b:398060672
TEST: `emerge-brya coreboot chromeos-bootimage`, flash and boot mithrax
to recovery screen and verify it can detect USB recovery stick in USB-C
ports.
This reverts commit 9207621d23.
Change-Id: I453562ab5802c7b9e38b7555415747dd9205aacb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88596
Reviewed-by: Eran Mitrani <mitrani@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:368661724, b:434033860, b:407590653, b:398060672
TEST: `emerge-brya coreboot chromeos-bootimage`, flash and boot mithrax
to recovery screen and verify it can detect USB recovery stick in USB-C
ports
This reverts commit e638a113fa.
Change-Id: I6a6349515f6662d792cf2f069bc847effa33a400
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88595
Reviewed-by: Eran Mitrani <mitrani@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After crash data extraction, the records are cleared and reinitialized
to their default values. This is done using watcher interface instead
of BIOS mailbox commands because of low latency and efficiency.
Ref: LNL FAS 733648
BUG= b:None
TEST= iotools mmio_dump 0x9c199d40 0x10 - PMC
0x000000009c199d40: 0xdeadbeef 0xdeadbeef 0xdeadbeef 0xdeadbeef
iotools mmio_dump 0x9c1d0058 0x10 - CPU
0x000000009c1d0058: 0xcafecafe 0xcafecafe 0xcafecafe 0xcafecafe
Initial 8 bytes of header are zeroes - indicating that both header
and crashlog data buffer are cleared
Change-Id: I8a36e091f61833067caf9e9f94ba79149e699d68
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Fix the ACPI HID and description for Goodix touchpad.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS and check the touchpad name in evtest.
Change-Id: I44b75841034a2004c62a577e60c630cc0e430fc8
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88461
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The I2C2 and I2C3 ports are unused. This patch removes them from overridetree.cb as they are already turned off in chipset_wcl.cb.
BUG=b:434127691
Change-Id: I8c00f7c96915a1a11b848af5ea128900fb5a16db
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88562
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the 2 new Samsung memory support.
DRAM Part Name Vendor Model ID to assign
K3KL6L60GM-MGCT Samsung LPDDR5X 4 (0100)
K3KL8L80EM-MGCU Samsung LPDDR5X 5 (0101)
BUG=b:426427376, b:432169883
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Change-Id: Ib707e2e482dc90bc02d73bd0fcda62630bacf1b5
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88449
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch enables QcLib execution for DDR and PMIC initialization.
SHRM and AOP firmware metadata are passed from coreboot to QcLib via
the interface table. On first entry, QcLib authenticates SHRM metadata
through TME and brings SHRM out of reset. Upon re-entry, QcLib forwards
AOP metadata to TME for authentication and brings AOP out of reset.
TEST=Verified QcLib boot (DDR Init, SHRM/AOP authentication & out of
reset flow) on google/bluey.
Change-Id: I4b726d5066ca807bf9d4df70f275e5dd991520cc
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch adds support to pack aop_meta into CBFS and load QcLib DTB,
SHRM metadata, and AOP metadata. It also populates the QcLib interface
table with these information for firmware authentication and execution.
TEST=Verify presence of AOP metadata file in the CBFS and QcLib
interface table content.
Change-Id: I1a74d9ffbfc10023b0e5610d54218909b18efa01
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88486
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable PCIE init for bluey board and update device pci node.
Remove unused pci 4.0 node(WLAN).
TEST= Verified that link is enumerated and NVMe is accessible via PCIE.
Change-Id: I7ad4a9409ff0465b45b8bb1f3e005bf9f83f2c42
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88535
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to enable QMP PCIe 4.0 PHY 2x2/1x4 lanes.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST= Verified that link is enumerated and NVMe is accessible via PCIE.
Change-Id: I9dd9a5340f28326ebabf12489c11e7f73f2c8d2f
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88583
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Enable QMP PCIe 4.0 PHY 2x2/1x4 lanes.
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST= Verified that link is enumerated and NVMe is accessible via PCIE.
Change-Id: I8a3cb1b21e712e588f641f70c040a2334faf0031
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88543
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The ISH GPIO pads for `ISH_GP_x` (GPP_B04, GPP_B05, GPP_B07, GPP_B08,
GPP_B22, GPP_B23) were previously configured in the generic gpio_table.
This commit moves their configuration to the `ish_enable_pads` and
`ish_disable_pads` structures within `fw_config.c`.
This change ensures that these ISH-specific pads are only configured
when the ISH is enabled, aligning with best practices for power
management and reducing potential conflicts when ISH is not in use.
BUG=b:396557201
TEST=Able to build and boot google/fatcat w/ ISH enable and/or disable.
Change-Id: I4ef896d220fbe5f9c042c4d9df97d32ac238cbc5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The GPP_B06 pin configuration for ISH_GP_2_SNSR_HDR is never required
for the Panther Lake SoC/ISH. This commit removes the obsolete entry
from the GPIO table, streamlining the configuration.
BUG=b:396557201
TEST=Able to build and boot google/fatcat.
Change-Id: I3f38c52a305d14e21c7fcf2dfb943133ae4a7e45
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
We use internal bypass for kaladin, so remove the external bypass settings
BUG=b:432378989
TEST=Flash and boot up kaladin, test that DUT can enter S0ix
Change-Id: I84207a21f15de2df813387e16065688f409b2523
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
GPP_F18 is the correct wake on touch GPIO, which overrides GPP_DW0_18.
Platform Mapping Document : Rev0p86
BUG=b:394208231
TEST=Touchpad works on ocelot RVP
Change-Id: I4ea9c36a371d69f829ba64bfeb35ab9afccf1e06
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88540
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board came virtually rebranded from a specific German OEM called
Wortmann AG and was identified as "TERRA_PC/H81M-D2W" model: 1009381.
It however ships a GIGABYTE GA-H81M-D2W rev 1.0 branded motherboard
which is extremely similar to a Retail GIGABYTE GA-H81M-D2V rev 1.0.
The only obvious differences are the onboard video outputs, its serial
connectivity and total abscence of it on the GIGABYTE support website.
- GA-H81M-D2W
DVI-D + DVI-I + serial port header on motherboard
- GA-H81M-D2V
DVI-D + VGA + DB9 serial port connector on backplate
Mainboard: GIGABYTE GA-H81M-D2W rev 1.0
Pure autoport (initial commit) doesn't boot, second patch brings up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, PCIe fixes enabling onboard LAN and other PCIe slots
and some IT8625E superio code from a other coreboot port made most
ITE8620E superio related functions work, especially WDT otherwise this
board resets every couple of seconds! Autoport did log hda codec / pins
but it didn't include them in the hda_verb.c, so I added them manually
which also fixes pcspkr (beep codes, not soundcard connected).
Flash instructions:
Internal flashing using flashrom works on OEM and when running coreboot
using the following command: flashrom -p internal -c "MX25L6473F" -w ROM
An external flasher ch341a_spi (3.3v mod) used with a SOIC 8 pomona
probe to recover the MX25L6473F in situ also works without issues. Only
the power of the USB programmer was used, and the board's main PSU was
disconnected during external flash!
Tested:
- coreboot 25.06-77-g812d0e2f626d as base
- EDK2 (MrChromebox/2502)
- SeaBIOS 1.16.3
- Broadwell mrc.bin (tidus)
- Haswell mrc.bin (peppy used for all mrc.bin noted testing)
- Haswell NRI
- libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
- DVI-D & DVI-I (VGA) all work during POST, BOOT and OS
- Pentium G3220 / Xeon E3-1225 v3 / Xeon E3-1231 v3
- RAM single and dual slot 2GB/4GB/8GB mixed DDR3 DIMMS max 6, 8, 16GB
(NRI & mrc.bin)
0/2: 2GB DDR3-1333 - Kingston 99U5458-001.A00LF (2010-W29)
0&2: 4GB DDR3-1600 - Kingston 9905402-174.A00G (2015-W33)
0/2: 2GB DDR3-1600 - Micron 8JTF25664AZ-1G6M1 (2013-W37)
0/2: 4GB DDR3-1600 - Samsung M378B5173BH0-CK0 (2013-W30)
(NRI single DIMM won't mix with others)
0/2: 8GB DDR3-1600 - SK Hynix HMT41GU6MFR8C-PB (2023-W20)
(ECC UDIMM, mrc.bin only, see NRI note below)
0&2: 4GB DDR3-1600 ECC - Kingston 9965432-051.A00LF (2013-W19)
0&2: 8GB DDR3-1866 ECC - Micron 18JSF1G72AZ-1G9E1 (2013-W29)
- Fedora MATE 42 (Kernel 6.14)
- KDE NEON 6.4 (Kernel 6.11)
- MS Windows 10 / 11
- Audio Outputs both DVI > HDMI, Headphone, Line Out (left&right chan.)
- Audio Input Line In (back)
- pcspkr
- USB2/3 all Intel ports
- SATA 4 ports
- PCIe slots (16x 5GT/s & both 1x 5GT/s)
- iGPU (plus dGPU as in dual GPU work both with mrc.bin / Haswell NRI)
- dGPU (nVidia GeForce GT640-2GD3 2.5GT/s / Radeon HD7770-1GB 5GT/s)
- Realtek RTL8111F onboard Gb LAN
- Wake on LAN
- HWM shows both fan speeds and voltages
- PS/2 port (both Keyboard and Mouse with Y splitter cable)
- Serial port header (coreboot console & OS)
- PowerButton (Poweron/Poweroff/Wake)
- ResetButton
- LEDs HDD & POWER (off during suspend)
- Shutdown/Reboot/Suspend
- Strip down the Intel ME/TXE firmware (make menuconfig) see ME note!
- Disabling ME HECI (manually remove from devicetree.cb) see ME note!
- flashrom -p internal -c "MX25L6473F" #read & write
Not tested:
- Audio Inputs Front & Back Microphone Ports
- parallel port header
- USBDEBUG
- VBIOS
Not working:
- Disable Intel ME PCI interface (make menuconfig)
- USB2/3 all VIA VL805 backpanel ports
FD layout note:
The original OEM firmware ships a BIOS region that seem to use the
whole firmware:
00000000:00000fff fd
00000000:007fffff bios
00001000:001fffff me
Although coreboot works fine with this flash descriptor layout it is
mandatory to flash a complete image! Replacing only a specific region
like the BIOS region when relying on --ifd will confuse flashrom and
trash the flash chip's contents! As a temporary measure one can use
--layout to flash a specific region using the following layout:
00000000:00000fff fd
00001000:001fffff me
00200000:007fffff bios
Permanently changing the flash descriptor layout to look like this will
solve flashing specific regions and remains a valid option since it
cannot break GIGABYTE its DualBIOS feature since its absent.
NRI note:
EDK2 shows 0GB instead of the actual RAM amount installed. While using
Haswell mrc.bin EDK2 shows the correct amount of RAM. The earlier noted
RAM modules have also been tested using NRI in Memtest86+ v7.20 which
still correctly displays and test the total amount of RAM.
ECC UDIMMs currently do not work on this board because NRI does
not check whether the board / chipset support ECC. This results
in RCVET failures for the ECC bytelane (byte 8). Eventually this
will be fixed in NRI. Haswell mrc.bin works as expected.
ME note:
Neutering the ME will let the system still function correctly, unless
you include EFFS and FCRS partitions addressed by ME_CLEANER_ARGS:
"-S --whitelist EFFS,FCRS"
Failing to supply these ME partitions will cripple superio functions as
in serial output (breaks coreboot serial console) and HWM fan and
voltage info goes random nuts while the fan stays at normal speed.
VIA VL805 note:
Without firmware loading (which is still unknown) and enabling it in the
devicetree.cb will give DMAR IOMMU errors therefore disabled by default!
The data.vbt blob was extracted using debugfs from the OEM F5 firmware
which enables both video outputs DVI-D and DVI-I (VGA).
Since this board is not listed on the GIGABYTE website, but it works
with the Retail GA-H81M-D2V F6 firmware I listed that one instead in the
board_info.txt. However I cannot confirm that this coreboot port also
works for the GA-H81M-D2V, it is good practice to at least check its
gpio values matching this port!
Change-Id: I80dc414a92d115099ec8966841af0cf22d5b1d09
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88412
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates GPP_F17 (CODEC_INIT_N) configuration to fix an issue
with the 3.5mm headphone jack on the I2S codec AIC not detecting
headphone plug/unplug events. Specifically, we need to configure GPP_F17 to have interrupt capability, edge detection to detect plug and unplug events, and power state persistence.
BUG=b:434208278
TEST=After booting to OS, plug and unplug a headphone to the I2S codec
add-in card, headphone is getting detected.
Change-Id: I1c662ec680d8175be5854c753ea1481d09afb561
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88564
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Becasue of requirement for VCCANA power from MBVR mode to FIVR mode,
so change ICCmax at VCCIN_AUX will be from 25A to 27A due to
internal VR.
BUG=b:417662158
TEST=Build and boot to OS at the rework motherboard and verfied by
power team.
Change-Id: Ie036412c0e435cfce39940de6bab363f9e875f42
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88558
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the machine shows circle icon instead of G icon in 'Setting'
->'Device'->'View keyboard shortcuts'.
So add MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD to enable G icon.
BUG=b:429495479
BRANCH=none
TEST= Build and boot to OS and enter 'Setting'->'Device'
->'View keyboard shortcuts' to see G icon.
Change-Id: I0a195c65fe2835f9be66c56fb7129851b3251b90
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88446
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
For the latest trulo projects: kaladin,pujjolo,pujjocent,
the original comment was too brief and led to some misunderstanding.
In the past years, only retimer has the SBU muxing function. Or said,
only retimer has Aux Orientation feature. So, 'no retimer' implies
Aux Orientation feature inside the processor is needed.
And now, the modern future PDC also has the Aux Orientation feature.
Not all "no retimer" cases require setting the override bit anymore.
The even numbered bits should be set only when there is no retimer and
the processor's Aux Orientation is still required.
(If set, the SoC inverts the orientation value coming from EC/PDC when
operating in flipped orientation.)
In the referenced issue tracker, the system has 'no retimer' and uses
a 'future PDC'. (The PDC has the Aux Orientation feature.)
Test results (DP + TCSS):
- 'tcss_aux_ori' = 0 + PDC sends orientation detected value -> PASS
- 'tcss_aux_ori' = 5 + PDC sends 'original' value -> PASS
- 'tcss_aux_ori' = 5 + PDC sends orientation detected value -> FAIL
(Fail means only display one side.)
This patch updates the comment to more accurately describe the expected
usage and avoid future confusion.
Refer doc#:
646929 TWL PDG
734752 TCSS Cookbook (MTL Backward/MTL/PTL/WCL)
627270 TWL Bios Spec
758766 MTL Bios Spec
766031 MTL PDG
BUG=b:4292672
BRANCH=none
TEST=Update coreboot device tree with different tcss_aux_ori value and
test the DP connection via TCSS on 2 orientations.
Change-Id: I3281110e522c53a35abf30fd1c372bb5ca18c10d
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88482
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP-T will help to cache bios region along with MTRR programming
by setting CodeRegionBase/CodeRegionLength, thus there is no need
for xeon_sp platforms to do it.
TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/archercity CRB
Check MTRR usage and below duplicated MTRR item get removed:
[DEBUG] 0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP
[DEBUG] 0x000fffffff000800: PHYMASK1: Length = 0x0000000001000000, Valid
Change-Id: Ia414a35c663f3aa1b02d944475a96e11d07a4f00
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Add support to increase the CPU clock frequency to 1.36(GHz).
The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Create an image.serial.bin and ensure it boots on X1P42100 and
CPU runs in 1.36GHz Frequency.
Change-Id: Ie51e032141bdfabf4c96b6891ec9f084561d97ff
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement the two functions defined as prototypes in gpio.h.
Allows to drop custom SMI handler code and use the generic function
from gpio.c instead.
Change-Id: I795af83374118d3fc2b46837b1822205c966fda6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88508
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of open coding what gpio_base2_value() does use the
function to get the GPIO states of the ID pins.
Change-Id: Ib09993998f7e8ee2a7e5295f49ed14058a095eb0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88505
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I8c83b3436818275958cd8eb8b1c0d7b235e0344c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88504
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to retrieve the value of multiple GPIOs
at once as integer value and use the generic function prototype
defined in include/gpio.h instead.
Therefore:
* select GENERIC_GPIO_LIB
* Stub gpio_input(). Existing code assumes the pin is input.
* Drop get_gpios() implementation
* Include new header file gpio.h
* Migrate pins from type int to gpio_t
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I2296ff72231b569c618295b36b95a89ffebb3a6e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88503
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I714eaf2115a455d327e6b2313dafd0e293bee8a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In order to use the common gpio.h header file typedef gpio_t in
soc/gpio.h for Intel common code, Intel lynxpoint and Intel broadwell.
Change-Id: I2049a2cfd75c60d00bdd564b294808760b6aff7f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Include the missing header stdbool.h
Fixes compilation error
hybrid_graphics.h:6:28: error: unknown type name 'bool'
while refactoring some code.
Change-Id: I96f7255049cd9e24d74838a173e920a00636b09e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88546
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When moving headers compilation can fail as pmh7.h is missing
the include for type bool. Add the missing include to make sure
future code refactoring works.
Fixed the error:
src/ec/lenovo/pmh7/pmh7.h:27:1: error: unknown type name 'bool'
Change-Id: Ib0a2489a0c461bf021168e98737ecb6062caa696
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename config options 'USE_DDRx' to 'DRAM_SUPPORT_DDRx' to make them
less clunky, and in preparation to expand their use inside SoC code.
Change-Id: Ie6edd730c5cbad679a90fcf7989a942d9b2dd3d8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <yuchi.chen@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update hda_verb table for pujjocento to optimize noise floor.
BUG=b:433647377
TEST=emerge-nissa sys-boot/coreboot sys-boot/chromeos-bootimage
Verify that the noise floor on AP is less than -90 dB when
DUT plays mute.wav.
Change-Id: Ib8642a88bb707e99c3d459eb70a6fdf5562f4c75
Signed-off-by: lizheng <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88549
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kaladin need to set this config since we use unified firmware for UFS and non UFS skus
BUG=b:432579255
TEST=Flash and boot on every sku on kaladin
Change-Id: I5fa8f51776e6ba13e9003ea7913c2b4784b76217
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88475
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add DRAM part H58G56CK8BX146
BUG=b:432397864
TEST=Flash and boot to OS successfully on kaladin
Change-Id: Id880940d608c76b88e384ee2cbea03eec8e35b53
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88469
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves the shrm_fw_load_reset() API from the SC7280 specific
implementation to the Qualcomm common directory. This change enables
reuse of the API across multiple Qualcomm chipsets.
Change-Id: Ifab870b9aea7396e29fa93c999c29cf11ab0d199
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88545
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set `TPM_TIS_ACPI_INTERRUPT` to 49 (GPE0_DW1_17) for all ocelot
variants using `BOARD_GOOGLE_MODEL_OCELOT` instead of
`BOARD_GOOGLE_OCELOT`.
BUG=b:433177132
TEST=Able to boot Ocelot
Change-Id: I662e1b38530861da008cf54da4a31dd0ac6212c8
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
