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soc/qc/x1p42100: Enable QcLib, SHRM and AOP firmware load

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This patch enables QcLib execution for DDR and PMIC initialization.
SHRM and AOP firmware metadata are passed from coreboot to QcLib via
the interface table. On first entry, QcLib authenticates SHRM metadata
through TME and brings SHRM out of reset. Upon re-entry, QcLib forwards
AOP metadata to TME for authentication and brings AOP out of reset.

TEST=Verified QcLib boot (DDR Init, SHRM/AOP authentication & out of
reset flow) on google/bluey.

Change-Id: I4b726d5066ca807bf9d4df70f275e5dd991520cc
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Sasirekaa Madhesu 2025-07-18 15:54:21 +05:30 • committed by Subrata Banik
commit d79febf356
1 changed files with 14 additions and 2 deletions
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16
src/mainboard/google/bluey/romstage.c
View file

@ -1,12 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/stages.h>
#include <gpio.h>
#include "board.h"
#include <gpio.h>
#include <soc/aop_common.h>
#include <soc/qclib_common.h>
#include <soc/shrm.h>
void platform_romstage_main(void)
{
/* Placeholder */
void (*const fw_init_sequence[])(void) = {
shrm_fw_load_reset,
qclib_load_and_run,
aop_fw_load_reset,
qclib_rerun,
};
/* Executing essential firmware loading */
for (size_t i = 0; i < ARRAY_SIZE(fw_init_sequence); i++)
fw_init_sequence[i]();
/*
* Enable this power rail now for FPMCU stability prior to