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mb/google/trulo/var/kaladin: Update USB2 driving settings

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Update USB2 driving for all USB2 ports

BUG=b:419548309
TEST=Pass USB2 eye diagram test on kaladin

Change-Id: I947ec78de29e20f72122c1b84df4ee99e2655208
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Eren Peng 2025-07-25 09:17:54 +08:00 • committed by Matt DeVillier
commit 0a4bc79685
1 changed files with 51 additions and 6 deletions
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57
src/mainboard/google/brya/variants/kaladin/overridetree.cb
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@ -37,12 +37,57 @@ chip soc/intel/alderlake
# eMMC HS400
register "emmc_enable_hs400_mode" = "true"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch)
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch)
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A MB (6.4 inch)
register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb2_ports[0]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_39P35MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
.type_c = 1,
}"# Type-C0
register "usb2_ports[1]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_39P35MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
.type_c = 1,
}"# Type-C1
register "usb2_ports[2]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_39P35MV,
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
}"# Type-A
register "usb2_ports[5]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_39P35MV,
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
}"#UFC
register "usb2_ports[7]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
}"# Bluetooth port for PCIe WLAN
register "usb2_ports[9]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_FULL_BIT_PRE_EMP,
}"# Bluetooth port for CNVi WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3 Type-A port A0(MLB)