Disable S0ix power states at baseboard level.
TEST=Booted into linux and verified S0ix is disabled:
- FADT Low Power S0 Idle (V5) = 0
Change-Id: I34243137c8b06efa476dda74763d358f88bfe6a5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88956
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add scan_bus operation to fast_spi device operations to enable
discovery of statically defined child devices.
This allows device drivers such as drivers/pc80/tpm that are
physically connected to the fast_spi bus to be properly
enumerated and initialized during device tree scanning.
Without this change, child devices defined in devicetree under
fast_spi would not be discovered, preventing proper driver
binding and initialization.
Example devicetree configuration:
```
device ref fast_spi on
chip drivers/pc80/tpm # SPI TPM header
device pnp 0c31.0 on end
end
end
```
Without a .scan_bus hook in fast_spi_dev_ops, coreboot's
BS_DEV_ENUMERATE phase never creates the pnp 0c31.0 device. As a
result, in BS_DEV_RESOURCES you see, that the device PNP 0c31.0
is missing its function "read_resources":
```
(in BS_DEV_ENUMERATE)
[DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 11 msecs
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 1510 msecs
[SPEW ] scan_static_bus for Root Device done
... (in BS_DEV_RESOURCES)
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0
[ERROR] PNP: 0c31.0 missing read_resources
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0 done
[SPEW ] DOMAIN: 00000000 read_resources segment group 0 bus 0 done
[SPEW ] Root Device read_resources segment group 0 bus 0 done
[INFO ] Done reading resources.
```
With the implementation of scan_bus, the log shows that the resources
are allocated correctly:
```
(in BS_DEV_ENUMERATE)
[DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 11 msecs
[DEBUG] PCI: 00:00:1f.5 scanning...
[SPEW ] scan_static_bus for PCI: 00:00:1f.5
[DEBUG] PNP: 0c31.0 enabled
[SPEW ] scan_static_bus for PCI: 00:00:1f.5 done
[DEBUG] scan_bus: bus PCI: 00:00:1f.5 finished in 14 msecs
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 1536 msecs
[SPEW ] scan_static_bus for Root Device done
... (in BS_DEV_RESOURCES)
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0
[SPEW ] dev: PNP: 0c31.0, index: 0x0, base: 0xfed40000, size: 0x5000
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0 done
[SPEW ] DOMAIN: 00000000 read_resources segment group 0 bus 0 done
[SPEW ] Root Device read_resources segment group 0 bus 0 done
[INFO ] Done reading resources.
```
TEST=Verified on Siemens mc_rpl1 mainboard. TPM device properly
enumerated with scan_bus implementation.
Change-Id: I4049d2d3cd5132362a7efd551dc9dd78cd24b9eb
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88966
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Disable DPTF for mc_rpl platform. In this context, the DPTF
configuration is removed as well. DPTF is deactivated to improve
realtime performance.
Change-Id: I5f9c2d1d82e9c18eafb9761df87a0709bded5964
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This file contains functions related to PCIe and SMM, and so it's
needed by bootblock and ramstage, and possibly romstage. It's not needed
by SMM, and in a follow-up, the SMI handler will define `smm_region`,
causing a function redefinition error.
As this file isn't needed in SMM, and the SMI handler's function
will work for this board too, as it works for all silicon (it returns
values populated during ramstage, by board/silicon implementations
of the function), drop this compilation unit from SMM.
Change-Id: I0195e7d42b0669d675879fb4d2596aa4607095b9
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88995
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PcieRpLtrEnable[] is a boolean, so use true false.
Change-Id: I3ccc64d7bb1a756efe8fc109c51c029a5483c316
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Increase WAIT_AUX_READY_TIME_MS from 1 ms to 3 ms fix a 20s timeout bug
on Google/Cherry/Tomato and possibly other MediaTek Chromebooks
introduced in commit 6ba2df9be5 (soc/mediatek/common: Use polling to
reduce eDP HPD wait time).
Change-Id: I6f41c3733e67c85e4aea3ce3b641a98cad94715c
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88991
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
FSP sets the MemoryType to 0x2 (MEMORY_TYPE_UNKNOWN) when a DIMM is not
present in a given slot, so skip parsing of any DMI records with that
type set.
TEST=build/boot out-of-tree Starlabs Cezanne-based board with a single
sodimm installed, verify the DMI record for the empty slot is not
parsed/inserted into the SMBIOS tables.
Change-Id: I683c7bf65cc261b6a4fc4cb74e7b4b5f96283f61
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88974
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.
Mirrors change previous done for Mendocino and newer SoCs.
Change-Id: I6790648da3724a06a127c1cef939366588668440
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Add a Kconfig to enable mainboards to select SERIRQ_CONTINUOUS_MODE,
which will be used by a to-be-added Cezanne-based Starlabs Starbook
variant in a subsequent commit.
Change-Id: Ia4da699e836e8e3ca408b4b5744320723e17ca62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
According to the datasheet and the LCD team’s response, increase Touch
IC enable delay time to resolve touch failure after resume.
BUG=b:441010546
TEST=Checked the waveform and suspend stress test, both checked OK.
Meet seconds_system_resume < 0.5 sec, boot time < 1.3 sec.
Change-Id: I778fd79f7bad3ad1873880b7412c0c49dcb40b1f
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This change disables the C1E (Enhanced Halt State) power saving feature
by clearing bit 1 in the MSR_POWER_CTL register. Disabling C1E prevents
the processor from automatically transitioning to a lower
voltage/frequency when all cores are halted, improving deterministic
behaviour.
For this platform, disabling C1E is always required, so the direct MSR
approach avoids FSP reliability issues and configuration complexity
that would come with using the existing devicetree "enable_c1e"
parameter.
TEST=Booted into OS and verified register MSR_POWER_CTL Bit 1 cleared:
- Used rdmsr tool: rdmsr 0x1FC showed bit 1 = 0
- Confirmed across all CPU cores
Change-Id: If076f0bb42f3a0d4b8f895703e88eaf145e4a762
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88964
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Remove unused implementation files and declarations:
- Delete ramstage.c containing DPTF power limit configuration
- Remove corresponding ramstage.c reference from Makefile.mk
- Remove unused ADL board ID enumeration in variants.h
- Remove cpu_power_limits structure and variant_update_power_limits()
- Remove variant_devtree_update() function and its weak implementation
The removed code was related to device tree updates and power limit
configurations that are not used by this mainboard.
Change-Id: I1b1c742a4b62022b91de8215d30a4df4f8cf68f0
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88962
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the CPU power limits configuration at the variant level to use 28W
for PL1, PL2. Set PL4 to 64W. This ensures consistent thermal
performance and power management behaviour.
Change-Id: I355f12ad66e9682f3d50356028baea01b42bffa3
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88961
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the moonstone variant of the fatcat reference board by copying
the kinmen files to a new directory named for the variant.
BUG=b:441010542
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_MOONSTONE
2. Run part_id_gen tool without any errors
Change-Id: Iad11c892270f6abc53dee12366691a8c987879f0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88978
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some legacy devices need to have the master bit set in the PCI config
due to old drivers not setting it correctly. Set the master bit if the
feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE.
This implementation is similar to the approach used in an earlier
Siemens platform, as implemented in commit 78ec750610
("mb/siemens/mc_ehl: Enable master bit in PCI config space if allowed").
TEST=Confirmed bus master enabled via lspci after boot.
Change-Id: I6d358ba7147860fd1383abe667a7006d9a30d542
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88963
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable Intel Turbo Boost on this platform as a first step toward
consistent frequency behavior. This platform requires deterministic
performance characteristics rather than dynamic frequency scaling.
TEST=Boot into OS, read MSR 0x1A0 (IA32_MISC_ENABLE) and verify that bit
38 (Turbo Disable) is set.
Change-Id: I6e89cdaaa56b5e5c70461ac67159c0fc3975a429
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
One of my previous commits attempted to simplify azalia_codec_init(),
but resulted in illogical code which also introduced a bug in certain
cases.
To summarize, codec_is_operative() tells the controller to get the
vendor ID of a specific codec. While doing so, this also checks how the
controller and codec respond to see if they are functioning. However, we
read the response in azalia_codec_init(). Therefore, these functions
must be called sequentially in order to initialize the codecs correctly.
In certain cases, we would attempt to read the response without
requesting the vendor ID in the first place. This possibly caused
these verbs to not get loaded at all.
These are the areas affected by the bug:
- northbridge/intel/haswell/minihd.c
- soc/intel/broadwell/minihd.c
TEST=Verbs were loaded on HP ProBook 450 G3
Fixes: 516d05f43d ("device/azalia: Separate codec checking and initialization")
Change-Id: I82ada9e6eca0539b854b5bc61f6f7a88ffd1cdc5
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88918
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a purely cosmetic change to make things slightly more easier to
read. We also only add the IDs which are actively used in the codebase.
TEST=Timeless build produces identical binaries
Change-Id: I4ec0a570020059c85768bab913dff1ba1977e9f9
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88917
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Set the active core configuration for the processor on this variant to
use 4 P-cores and 0 E-cores. This ensures that only the performance
cores are enabled, which matches the intended use case for this specific
board variant.
Change-Id: If79b13fea16bcd369feb438aab4ab11dd63d4fab
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88958
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the CPU does not control any fans and the mainboard does not
implement a charger, remove all unnecessary DPTF UPDs. DPTF will be used
for limitting PL1 and PL2 in the future.
Change-Id: I22e1167cb2986f5c56ff6085236792adbb9a19cc
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88954
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board does only use SATA Port 0 and SATA Port 1. The rest is
disabled. In addition, power management features like DevSlp and
Aggressive Link Power management are not supported on this motherboard
and are deactivated accordingly.
TEST=Verified SATA config: `dmesg | grep -i "sata link"` shows ports
0-1 active at 3.0 Gbps (Gen2 limit).
Change-Id: I4567328c25f195fac8edc02518a6a812922f48e5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Activate NC_FPGA driver in the baseboard as it will be used by
all variants.
Change-Id: Ia6538dfc752f661411687d5c5cf635e6d4c0ac16
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88950
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rewrite suspicious register handling as per reference code. Proper
handling of the value in the RPC register needs some IOBP operations,
and will be done in a follow-up once `pch_iobp_update` can be used.
TEST=Still boots on Lenovo X220.
Change-Id: I7cf8851e98e3971593734dc2a46f7e0b43d8cdca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
PcieRpClkReqSupport[] is a boolean, so use true/false.
Change-Id: I541ac5361dc0a929459edef7bb1f49c57b137c14
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86281
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit enables memory bandwidth compression for Integrated Graphics
Device (IGD) when IGD is active. This change intends to improve graphics
performance.
BUG=b:431221875
TEST=On a Fatcat device, activating memory bandwidth compression leads
to graphics performance improvements ranging from 20% to 65% on
some graphics workloads.
Change-Id: Ia74fb6bac880a5eb9fe833f071bd129e69345d28
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88910
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
This commit reserves memory resources associated with the memory
bandwidth compression functionality for Intel Integrated Graphics
Devices (IGD). The reservation is achieved by identifying the memory
region in the Resource Hand-Off Blocks (HOB) through a specific GUID,
provided in the FSP integration guide, and then marking it as
reserved. This ensures that the memory compression functionality can
operate without interference from other processes.
BUG=b:441695812
TEST=On a Fatcat device with the MemoryBandwidthCompression UPD set to
1, coreboot logs show both the detection of the HOB and the related
memory resource marked as reserved.
[DEBUG] Memory Compression HOB found: base=0x100000000
length=0x02400000
[...]
[DEBUG] 19. 0000000100000000-00000001023fffff: RESERVED
Change-Id: I21f247dd8aaa88d4ae4da70eb78f7decc1793777
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
When the passed `blob` is not a valid FDT, the memory allocated for
`tree` should be freed. Move the allocation after the fdt_is_valid()
check to avoid the problem.
Also remove the unnecessary cast to 'const struct fdt_header *'.
Change-Id: If591172cd511ae2a1ca9c26f2addef8d67fd0b69
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88948
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
On MT8189, UFS power is enabled by default. For SKUs that use eMMC for
storage and do not need UFS, it is necessary to disable UFS power;
otherwise, the system will fail to suspend properly. Disabling UFS
power in these cases both saves power and ensures correct suspend
functionality.
BUG=b:430421429
BRANCH=skywalker
TEST=Suspend flow works correctly, and SoC power consumption is 34 mW,
meeting expectations on Anakin.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ie932a939f663e159e098fd13c7e26e9a2089e7bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88977
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On MT8189, UFS power is enabled by default. For SKUs that do not use UFS
as storage, keeping UFS power enabled can cause suspend failures and
unnecessary power consumption. This change implements a UFS power-off
API to ensure UFS can be properly powered down on non-UFS SKUs.
BUG=b:430421429
BRANCH=skywalker
TEST=Suspend flow works correctly, and SoC power consumption is 34 mW,
meeting expectations on Anakin.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Irving-ch Lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: Ib5ccbeaf951c3a095905e472bc096eeb2dee47a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88976
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Moves the MTRR setup for graphics memory (GMADR) from the
`soc_load_logo_by_coreboot()` function to `do_silicon_init()`. This
refactors the logic into a new helper function,
`soc_mark_gfx_memory()`, which acquires a temporary Write-Combine
(WC) MTRR.
The MTRR is now configured earlier in the silicon initialization
process, making the setup and cleanup independent of the
`soc_load_logo_by_coreboot()` function itself.
This improves FSP-S performance and ensures the MTRR is correctly
managed within the silicon initialization flow which was earlier
missed when platform selects `USE_COREBOOT_FOR_BMP_RENDERING` aka
rendering the BMP logo using coreboot driver and not using FSP driver
logic.
The cleanup of the MTRR is also moved to `do_silicon_init()` to pair
with the earlier setup.
TEST=Successfully boot to OS on google/fatcat using coreboot for logo
rendering.
w/o this patch
```
963:returning from FspMultiPhaseSiInit 1,164,839 (123,244)
```
w/ this patch
```
963:returning from FspMultiPhaseSiInit 1,143,974 (115,443)
```
Change-Id: I5da3178c622f5fd6cb3d7f3f574e59f9ed5a5b3d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88982
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch increases the hardcoded MTRR region size from 16 MiB to 32
MiB. This ensures a larger portion of memory is cached after the DRAM
phase, which helps in avoiding performance issues in memory-constrained
boots like the pre-DRAM stage. This change is crucial for optimal system
performance.
TEST=Able to boot google/fatcat and save 13ms of the boot time.
w/o this patch:
```
31:device enumeration 1,183,804 (13,341)
```
w/ this patch:
```
31:device enumeration 1,159,612 (359)
```
Change-Id: I25463f1b9e3b82b1a05a8fb7a44df4d188b4731a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88971
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit addresses incorrect Thermal Design Power (TDP) mappings for
Panther Lake-U SKUs. Both 15W and 25W TDPs are now correctly mapped to
the same Power Limit configurations, ensuring consistent handling of
these SKUs.
Below is the collection of documents utilized to address this issue:
1. 815002 Panther Lake H Processor - External Design Specification
Revision. 1.52
2. 813278 Panther Lake H Power Map - Rev 1p6
BUG=None
TEST=Do not see error log "Could not find the SKU power map" and warning
"Skipped power limits configuration for SA PCI ID: 0xb003"
Change-Id: I995183a04b47967dd22ee6f4f3820da7eeb175bf
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88930
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
This patch removes redundant SNDW GPIO mapping that was already present
in fw_config.c and applied as per FW_CONFIG.
TEST=Verify that ocelot builds without any error
Change-Id: I8ba76d77764d4b9cec22c79b977ad9e486ae804e
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88937
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
fw_config
This commit implements `mainboard_is_hda_codec_enabled()` for the
Google Ocelot mainboard variant. This overrides the default weak HDA
common initialization.
Change-Id: I11f9d8ae00d1a3d7f03e068aa3980ecd98a47ecd
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88933
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on QEMU with ECC. Use mmap_helper to handle loading of compressed
ramstage. Bootblock fits in SEEPROM with both console and LZ4
romstage compression, but not with verbose CBFS debug messages.
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I91c72c52849eb1e3fafe43390351537d04382e46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
On PPC64 each address is logically OR'ed with HRMOR (Hypervisor Real
Mode Offset Register) before it is dispatched to the underlying memory,
meaning that memory space overlaps at the least significant bit set in
HRMOR. coreboot is entered with HRMOR = 4GB-128MB both on hardware
(when started by hostboot bootloader) and in Qemu in hb-mode. This means
that memory overlaps every 128MB in this particular case. HRMOR can be
explicitly ignored when MSB of an address is set, but this would require
using different memory model for linking.
If we zero HRMOR in bootblock, linking can be done against real address.
This greatly simplifies memory layout and allows to forget about HRMOR
from that point on.
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Change-Id: I0170463968c91b943c4b0dc15fe73fa616a164da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67067
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I found a space(' ') that was probably added unintentionally
in the cbmem_run_init_hooks().
So i deleted it to make the code cleaner.
P.S. It seems that clang-format can correct issues like it but
clang-format is unusable currently. See util/lint/check-style.
And this style issue of the code hasn't been corrected since 2015.
So i decided to correct it manually for now.
Change-Id: I788047d51c1f2586c3480efc4a31848e287c5894
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88325
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is cherry-picked from:
https://github.com/Dasharo/coreboot.git
Branch: protectli_vault_kbl/release
Original commit hash: b2b0a2bafbbe9be640f0fd0d02d85c81c90b796b
Then it was modified after code review, to:
* make it configurable
* remove code duplication
Signed-off-by: Purdea Andrei <andrei@purdea.ro>
Change-Id: I1350df3407aaa9b1fdaf9383972fac3a708bea96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88221
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
At first glance the order of IOHCs seems peculiar. However, the
order is not random. Explain the reasoning of the IOHC order in the
comment.
Change-Id: Ic8e567d48a0f8d95ff9785cdd0c5489ea3016f1a
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
When SOC_AMD_COMMON_BLOCK_PSP_SMI is enabled probe for the SPI
flash before actually servicing PSP SMI requests. This allows
to check the SPI flash status register in the following SMIs
if the flash is busy without needing to probe it first.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Iff01d0ea46f1bd2c32dbf4c4f65f9851fdf024e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88436
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Since the PSP SMI can trigger any time, even when ring 0 uses the SPI
controller backup and restore the SPI MMIO space in SMM, making
sure to not corrupt ongoing SPI transfers in ring 0.
There's still the possibility of register clobbering when the SPI
controller was busy and became ready before the SMI handler could
check the status bit.
TEST: Booted on AMD glinda with CONSOLE_SERIAL enabled and observed
no boot failure.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Iaa5270d93d4934b2e7ebdf04151f1c0d9f57cfb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88435
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
