mb/siemens/mc_rpl: Disable C1E state via MSR_POWER_CTL

This change disables the C1E (Enhanced Halt State) power saving feature
by clearing bit 1 in the MSR_POWER_CTL register. Disabling C1E prevents
the processor from automatically transitioning to a lower
voltage/frequency when all cores are halted, improving deterministic
behaviour.

For this platform, disabling C1E is always required, so the direct MSR
approach avoids FSP reliability issues and configuration complexity
that would come with using the existing devicetree "enable_c1e"
parameter.

TEST=Booted into OS and verified register MSR_POWER_CTL Bit 1 cleared:
- Used rdmsr tool: rdmsr 0x1FC showed bit 1 = 0
- Confirmed across all CPU cores

Change-Id: If076f0bb42f3a0d4b8f895703e88eaf145e4a762
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88964
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>

src/mainboard/siemens/mc_rpl/mainboard.c

@@ -12,6 +12,8 @@
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <soc/msr.h>
 
 #define MAX_PATH_DEPTH		12
 #define MAX_NUM_MAPPINGS	10
@@ -94,6 +96,15 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->TurboMode = 0;
 }
 
+static void disable_c1e(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_POWER_CTL);
+	msr.lo &= ~(1 << 1);
+	wrmsr(MSR_POWER_CTL, msr);
+}
+
 static void mainboard_final(void *chip_info)
 {
 	struct device *dev;
@@ -104,8 +115,9 @@ static void mainboard_final(void *chip_info)
 		if (dev)
 			pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 	}
-}
 
+	disable_c1e();
+}
 
 static void mainboard_init(void *chip_info)
 {