coreboot/src
Kilian Krause 993a9c9e14 mb/siemens/mc_rpl1: Configure SATA Ports
This board does only use SATA Port 0 and SATA Port 1. The rest is
disabled. In addition, power management features like DevSlp and
Aggressive Link Power management are not supported on this motherboard
and are deactivated accordingly.

TEST=Verified SATA config: `dmesg | grep -i "sata link"` shows ports
0-1 active at 3.0 Gbps (Gen2 limit).

Change-Id: I4567328c25f195fac8edc02518a6a812922f48e5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2025-08-30 13:49:20 +00:00
..
acpi drivers/crb/tpm: Add new method to retrieve base address 2025-07-02 16:15:09 +00:00
arch soc/power9/rom_media.c: find CBFS in PNOR 2025-08-28 20:14:01 +00:00
commonlib commonlib/device_tree: Fix memory leak in fdt_unflatten() 2025-08-29 09:10:27 +00:00
console console/i2c_smbus: Allow to send data w/o register offset 2024-07-11 00:06:22 +00:00
cpu cpu/x86/mp_init: Refactor ICR wait logic 2025-08-19 20:56:58 +00:00
device device/device_util: Fix format specifier for DEVICE_PATH_GICC_V3 2025-08-15 19:00:14 +00:00
drivers drivers/intel/fsp2_0: Refactor for earlier graphics memory WC MTRR 2025-08-29 04:33:07 +00:00
ec ec/starlabs/merlin: Add a "off" mode for the power LED 2025-08-24 20:23:40 +00:00
include include: Make DRAM an explicit region 2025-08-16 01:58:58 +00:00
lib src/lib/cbmem_common: Delete a space(' ') in the source code 2025-08-28 20:13:34 +00:00
mainboard mb/siemens/mc_rpl1: Configure SATA Ports 2025-08-30 13:49:20 +00:00
northbridge nb/intel/sandybridge/northbridge.c: Disable non-active PEG devices 2025-08-28 20:08:17 +00:00
sbom sbom: Fix build with merged bootblock and romstage 2025-07-07 14:29:29 +00:00
security security/vboot: Back up CMOS data later boot phase 2025-06-05 13:36:19 +00:00
soc soc/intel/pantherlake: Enable memory bandwidth compression for IGD 2025-08-29 16:03:46 +00:00
southbridge sb/intel/bd82x6x: Fix replay issues 2025-08-30 12:02:18 +00:00
superio src/superio/nuvoton: Add HWM initialization code 2025-06-11 13:31:25 +00:00
vendorcode vc/intel/fsp: Update PTL FSP headers to FSP 3272_04 2025-08-19 11:29:21 +00:00
Kconfig security/vboot: Back up CMOS data later boot phase 2025-06-05 13:36:19 +00:00