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mb/siemens/mc_rpl1: Configure SATA Ports

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This board does only use SATA Port 0 and SATA Port 1. The rest is
disabled. In addition, power management features like DevSlp and
Aggressive Link Power management are not supported on this motherboard
and are deactivated accordingly.

TEST=Verified SATA config: `dmesg | grep -i "sata link"` shows ports
0-1 active at 3.0 Gbps (Gen2 limit).

Change-Id: I4567328c25f195fac8edc02518a6a812922f48e5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Kilian Krause 2025-06-11 12:26:24 +02:00 • committed by Matt DeVillier
commit 993a9c9e14
2 changed files with 9 additions and 17 deletions
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17
src/mainboard/siemens/mc_rpl/devicetree.cb
View file

@ -13,22 +13,6 @@ chip soc/intel/alderlake
# Sagv Configuration
register "sagv" = "SaGv_Enabled"
register "sata_salp_support" = "1"
register "sata_ports_enable" = "{
[0] = 1,
[1] = 1,
[2] = 1,
[3] = 1,
}"
register "sata_ports_dev_slp" = "{
[0] = 1,
[1] = 1,
[2] = 1,
[3] = 1,
}"
register "s0ix_enable" = "true"
register "dptf_enable" = "true"
@ -130,7 +114,6 @@ chip soc/intel/alderlake
end
end
device ref crashlog off end
device ref sata on end
device ref p2sb on end
device ref smbus on end
end

9
src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
View file

@ -3,6 +3,14 @@ chip soc/intel/alderlake
# seen on J0 and Q0 SKUs
register "disable_package_c_state_demotion" = "true"
register "sata_salp_support" = "0"
register "sata_speed" = "SATA_GEN2"
register "sata_ports_enable" = "{
[0] = 1,
[1] = 1,
}"
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Port2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB
@ -128,5 +136,6 @@ chip soc/intel/alderlake
device pnp 0c31.0 on end
end
end
device ref sata on end
end
end