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mb/siemens/mc_rpl: Disable SaGv

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Disable SaGv at baseboard level to improve realtime performance.

Change-Id: I0fd587aa8beb0c86ba88553cfeddac786b4c8948
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Kilian Krause 2025-06-11 15:30:53 +02:00 • committed by Matt DeVillier
commit 66a3f2a1b1
1 changed files with 1 additions and 1 deletions
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src/mainboard/siemens/mc_rpl/devicetree.cb
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@ -11,7 +11,7 @@ chip soc/intel/alderlake
# FSP configuration
# Sagv Configuration
register "sagv" = "SaGv_Enabled"
register "sagv" = "SaGv_Disabled"
register "s0ix_enable" = "true"
register "dptf_enable" = "true"